Inventor · disambiguated record
Anatoly Koyfman
Also filed as: KOYFMAN ANATOLY · KOYFMAN ANATOLY ALBERT
10 granted patents·2 pending applications·70 citations·filing 2002–2019
86Inventor score
Technology areasG06F
Top patents by PatentIndex Score
12 records- 0186US8589892B2Verification of speculative executionFOURNIER LAURENT·Filed 2010·Granted Nov 19, 2013·16 cites·20 claims
- 0278US7370296B2Modeling language and method for address translation design mechanisms in test generationIBM·Filed 2004·Granted May 6, 2008·30 cites·25 claims
- 0375US8892386B2Method and apparatus for post-silicon testingADIR ALLON·Filed 2011·Granted Nov 18, 2014·5 cites·18 claims
- 0472US10026500B2Address translation stimuli generation for post-silicon functional validationIBM·Filed 2015·Granted Jul 17, 2018·2 cites·20 claims
- 0572US9633155B1Circuit modificationIBM·Filed 2015·Granted Apr 25, 2017·2 cites·20 claims
- 0663US8245164B2Method of verification of address translation mechanismsKATZ YOAV AVRAHAM·Filed 2009·Granted Aug 14, 2012·3 cites·20 claims
- 0761US8938646B2Mutations on input for test generationIBM·Filed 2012·Granted Jan 20, 2015·1 cites·15 claims
- 0856US7028067B2Generation of mask-constrained floating-point addition and subtraction test cases, and method and system thereforIBM·Filed 2002·Granted Apr 11, 2006·11 cites·21 claims
- 0948US11023366B2Diminution of test templates in test suitesIBM·Filed 2019·Granted Jun 1, 2021·0 cites·20 claims
- 1046US2008209160A1Device, System and Method of Verification of Address Translation MechanismsKATZ YOAV AVRAHAM·Filed 2007·Application pending·0 cites
- 1144US2014019929A1Partial Instruction-by-instruction checking on acceleration platformsIBM·Filed 2013·Application pending·0 cites
- 1238US8601418B1Instruction-by-instruction checking on acceleration platformsCHATTERJEE DEBAPRIYA·Filed 2012·Granted Dec 3, 2013·0 cites·16 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →