Inventor · disambiguated record
Anil Krishna
Also filed as: KRISHNA ANIL
24 granted patents·14 pending applications·135 citations·filing 2007–2017
94Inventor score
Top patents by PatentIndex Score
38 records- 0196US10108417B2Storing narrow produced values for instruction operands directly in a register map in an out-of-order processorQUALCOMM INC·Filed 2015·Granted Oct 23, 2018·42 cites·30 claims
- 0285US8914570B2Selective write-once-memory encoding in a flash based disk cache memoryBALAKRISHNAN GANESH·Filed 2012·Granted Dec 16, 2014·7 cites·16 claims
- 0383US8364898B2Optimizing a cache back invalidation policyIBM·Filed 2009·Granted Jan 29, 2013·12 cites·12 claims
- 0483US8078852B2Predictors with adaptive prediction thresholdAL-OTOOM MUAWYA MOHAMED·Filed 2009·Granted Dec 13, 2011·17 cites·20 claims
- 0582US9043556B2Optimizing a cache back invalidation policyIBM·Filed 2012·Granted May 26, 2015·6 cites·18 claims
- 0681US8103894B2Power conservation in vertically-striped NUCA cachesBALAKRISHNAN GANESH·Filed 2009·Granted Jan 24, 2012·11 cites·20 claims
- 0780US9262170B2Out-of-order checkpoint reclamation in a checkpoint processing and recovery core microarchitectureKRISHNA ANIL·Filed 2012·Granted Feb 16, 2016·7 cites·21 claims
- 0879US8200905B2Effective prefetching with multiple processors and threadsBELL GORDON BERNARD·Filed 2008·Granted Jun 12, 2012·10 cites·10 claims
- 0977US8438339B2Cache management for a number of threadsKRISHNA ANIL·Filed 2009·Granted May 7, 2013·9 cites·18 claims
- 1071US8140825B2Systems and methods for selectively closing pages in a memoryBALAKRISHNAN GANESH·Filed 2008·Granted Mar 20, 2012·5 cites·20 claims
- 1168US9851774B2Method and apparatus for dynamic clock and voltage scaling in a computer processor based on program phaseQUALCOMM INC·Filed 2016·Granted Dec 26, 2017·1 cites·29 claims
- 1268US8543767B2Prefetching with multiple processors and threads via a coherency busBELL GORDON B·Filed 2012·Granted Sep 24, 2013·3 cites·6 claims
- 1363US9081504B2Write bandwidth management for flash devicesBALAKRISHNAN GANESH·Filed 2011·Granted Jul 14, 2015·1 cites·6 claims
- 1461US10331447B2Providing efficient recursion handling using compressed return address stacks (CRASs) in processor-based systemsQUALCOMM INC·Filed 2017·Granted Jun 25, 2019·1 cites·24 claims
- 1559US8171220B2Cache architecture with distributed state bitsBALAKRISHNAN GANESH·Filed 2009·Granted May 1, 2012·1 cites·20 claims
- 1657US10551896B2Method and apparatus for dynamic clock and voltage scaling in a computer processor based on program phaseQUALCOMM INC·Filed 2017·Granted Feb 4, 2020·0 cites·36 claims
- 1755US8639886B2Store-to-load forwarding mechanism for processor runahead mode operationBELL GORDON·Filed 2009·Granted Jan 28, 2014·1 cites·18 claims
- 1855US8140767B2Cache management through delayed writebackBELL GORDON BERNARD·Filed 2009·Granted Mar 20, 2012·1 cites·14 claims
- 1951US8140758B2Data reorganization in non-uniform cache access cachesBALAKRISHNAN GANESH·Filed 2009·Granted Mar 20, 2012·0 cites·19 claims
- 2049US2013173849A1Write bandwidth management for flashdevicesBALAKRISHNAN GANESH·Filed 2012·Application pending·0 cites
- 2147US9471325B2Method and apparatus for selective renaming in a microprocessorQUALCOMM INC·Filed 2013·Granted Oct 18, 2016·0 cites·30 claims
- 2246US9424159B2Performance measurement of hardware acceleratorsIBM·Filed 2013·Granted Aug 23, 2016·0 cites·11 claims
- 2346US2009157968A1Cache Memory with Extended Set-associativity of Partner SetsIBM·Filed 2007·Application pending·0 cites
- 2444US2015268959A1Physical register scrubbing in a computer microprocessorQUALCOMM INC·Filed 2014·Application pending·0 cites
- 2543US10725782B2Providing variable interpretation of usefulness indicators for memory tables in processor-based systemsQUALCOMM INC·Filed 2017·Granted Jul 28, 2020·0 cites·20 claims
- 2643US10437592B2Reduced logic level operation folding of context history in a history register in a prediction system for a processor-based systemQUALCOMM INC·Filed 2017·Granted Oct 8, 2019·0 cites·45 claims
- 2741US2019087184A1Select in-order instruction pick using an out of order instruction pickerQUALCOMM INC·Filed 2017·Application pending·0 cites
- 2840US10635446B2Reconfiguring execution pipelines of out-of-order (OOO) computer processors based on phase training and predictionQUALCOMM INC·Filed 2015·Granted Apr 28, 2020·0 cites·33 claims
- 2939US2018081690A1Performing distributed branch prediction using fused processor cores in processor-based systemsQUALCOMM INC·Filed 2016·Application pending·0 cites
- 3039US2018081806A1Memory violation predictionQUALCOMM INC·Filed 2016·Application pending·0 cites
- 3139US2017371669A1Branch target predictorQUALCOMM INC·Filed 2016·Application pending·0 cites
- 3238US2019065060A1Caching instruction block header data in block architecture processor-based systemsQUALCOMM INC·Filed 2017·Application pending·0 cites
- 3337US2017060750A1Cache way prediction using partial tagsQUALCOMM INC·Filed 2015·Application pending·0 cites
- 3437US2017090508A1Method and apparatus for effective clock scaling at exposed cache stallsQUALCOMM INC·Filed 2015·Application pending·0 cites
- 3536US2008282029A1Structure for dynamic optimization of dynamic random access memory (dram) controller page policyBALAKRISHNAN GANESH·Filed 2008·Application pending·0 cites
- 3635US2017060593A1Hierarchical register file systemQUALCOMM INC·Filed 2015·Application pending·0 cites
- 3735US2008282028A1Dynamic optimization of dynamic random access memory (dram) controller page policyIBM·Filed 2007·Application pending·0 cites
- 3835US2012124291A1Secondary Cache Memory With A Counter For Determining Whether to Replace Cached DataACHILLES HEATHER D·Filed 2010·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →