Inventor · disambiguated record
Anand S. Murthy
Also filed as: MURTHY ANAND · MURTHY ANAND S
348 granted patents·239 pending applications·5,679 citations·filing 1999–2025
99Inventor score
Top patents by PatentIndex Score
587 records- 0199US11251281B2Contact resistance reduction employing germanium overlayer pre-contact metalizationINTEL CORP·Filed 2020·Granted Feb 15, 2022·5 cites·20 claims
- 0299US7662689B2Strained transistor integration for CMOSINTEL CORP·Filed 2003·Granted Feb 16, 2010·343 cites·34 claims
- 0399US6885084B2Semiconductor transistor having a stressed channelINTEL CORP·Filed 2003·Granted Apr 26, 2005·159 cites·12 claims
- 0499US6861318B2Semiconductor transistor having a stressed channelINTEL CORP·Filed 2003·Granted Mar 1, 2005·165 cites·11 claims
- 0599US6621131B2Semiconductor transistor having a stressed channelINTEL CORP·Filed 2001·Granted Sep 16, 2003·534 cites·20 claims
- 0699US6605498B1Semiconductor transistor having a backfilled channel materialINTEL CORP·Filed 2002·Granted Aug 12, 2003·338 cites·20 claims
- 0798US11923410B2Transistor with isolation below source and drainINTEL CORP·Filed 2021·Granted Mar 5, 2024·4 cites·23 claims
- 0898US9583491B2CMOS nanowire structureKIM SEIYON·Filed 2015·Granted Feb 28, 2017·28 cites·15 claims
- 0998US9349810B2Selective germanium P-contact metalization through trenchINTEL CORP·Filed 2015·Granted May 24, 2016·17 cites·20 claims
- 1098US9343559B2Nanowire transistor devices and forming techniquesINTEL CORP·Filed 2015·Granted May 17, 2016·25 cites·20 claims
- 1198US9224810B2CMOS nanowire structureKIM SEIYON·Filed 2011·Granted Dec 29, 2015·44 cites·23 claims
- 1298US9117791B2Selective germanium P-contact metalization through trenchGLASS GLENN A·Filed 2011·Granted Aug 25, 2015·38 cites·22 claims
- 1398US8847281B2High mobility strained channels for fin-based transistorsCEA STEPHEN M·Filed 2012·Granted Sep 30, 2014·47 cites·22 claims
- 1498US7402872B2Method for forming an integrated circuitINTEL CORP·Filed 2006·Granted Jul 22, 2008·141 cites·15 claims
- 1597US9859368B2Integration methods to fabricate internal spacers for nanowire devicesINTEL CORP·Filed 2016·Granted Jan 2, 2018·11 cites·15 claims
- 1697US9728464B2Self-aligned 3-D epitaxial structures for MOS device fabricationGLASS GLENN A·Filed 2012·Granted Aug 8, 2017·28 cites·30 claims
- 1797US9484447B2Integration methods to fabricate internal spacers for nanowire devicesKIM SEIYON·Filed 2012·Granted Nov 1, 2016·35 cites·9 claims
- 1897US9484432B2Contact resistance reduction employing germanium overlayer pre-contact metalizationINTEL CORP·Filed 2015·Granted Nov 1, 2016·14 cites·20 claims
- 1997US9437691B2Column IV transistors for PMOS integrationGLASS GLENN A·Filed 2011·Granted Sep 6, 2016·18 cites·25 claims
- 2097US9153583B2III-V layers for N-type and P-type MOS source-drain contactsGLASS GLENN A·Filed 2011·Granted Oct 6, 2015·28 cites·25 claims
- 2197US9012284B2Nanowire transistor devices and forming techniquesGLASS GLENN A·Filed 2012·Granted Apr 21, 2015·37 cites·28 claims
- 2297US8994104B2Contact resistance reduction employing germanium overlayer pre-contact metalizationGLASS GLENN A·Filed 2011·Granted Mar 31, 2015·41 cites·23 claims
- 2397US8901537B2Transistors with high concentration of boron doped germaniumMURTHY ANAND S·Filed 2010·Granted Dec 2, 2014·56 cites·25 claims
- 2497US8313999B2Multi-gate semiconductor device with self-aligned epitaxial source and drainCAPPELLANI ANNALISA·Filed 2009·Granted Nov 20, 2012·70 cites·14 claims
- 2597US7494858B2Transistor with improved tip profile and method of manufacture thereofINTEL CORP·Filed 2005·Granted Feb 24, 2009·104 cites·15 claims
- 2697US7195985B2CMOS transistor junction regions formed by a CVD etching and deposition sequenceINTEL CORP·Filed 2005·Granted Mar 27, 2007·98 cites·14 claims
- 2797US6949482B2Method for improving transistor performance through reducing the salicide interface resistanceINTEL CORP·Filed 2003·Granted Sep 27, 2005·100 cites·31 claims
- 2897US6797556B2MOS transistor structure and method of fabricationINTEL CORP·Filed 2003·Granted Sep 28, 2004·139 cites·21 claims
- 2997US6653700B2Transistor structure and method of fabricationINTEL CORP·Filed 2002·Granted Nov 25, 2003·144 cites·8 claims
- 3096US12021149B2Fin smoothing and integrated circuit structures resulting therefromINTEL CORP·Filed 2023·Granted Jun 25, 2024·2 cites·20 claims
- 3196US9812524B2Nanowire transistor devices and forming techniquesINTEL CORP·Filed 2016·Granted Nov 7, 2017·13 cites·20 claims
- 3296US9722023B2Selective germanium P-contact metalization through trenchINTEL CORP·Filed 2016·Granted Aug 1, 2017·9 cites·20 claims
- 3396US9627384B2Transistors with high concentration of boron doped germaniumINTEL CORP·Filed 2014·Granted Apr 18, 2017·12 cites·20 claims
- 3496US9064944B2Nanowire transistor with underlayer etch stopsKIM SEIYON·Filed 2013·Granted Jun 23, 2015·27 cites·14 claims
- 3596US9059024B2Self-aligned contact metallization for reduced contact resistanceGLASS GLENN A·Filed 2011·Granted Jun 16, 2015·25 cites·25 claims
- 3696US7732285B2Semiconductor device having self-aligned epitaxial source and drain extensionsINTEL CORP·Filed 2007·Granted Jun 8, 2010·41 cites·7 claims
- 3796US7682916B2Field effect transistor structure with abrupt source/drain junctionsINTEL CORP·Filed 2008·Granted Mar 23, 2010·31 cites·10 claims
- 3896US7338873B2Method of fabricating a field effect transistor structure with abrupt source/drain junctionsINTEL CORP·Filed 2006·Granted Mar 4, 2008·28 cites·5 claims
- 3996US6887762B1Method of fabricating a field effect transistor structure with abrupt source/drain junctionsINTEL CORP·Filed 1999·Granted May 3, 2005·141 cites·10 claims
- 4096US6812086B2Method of making a semiconductor transistorINTEL CORP·Filed 2002·Granted Nov 2, 2004·136 cites·22 claims
- 4196US6214679B1Cobalt salicidation method on a silicon germanium filmINTEL CORP·Filed 1999·Granted Apr 10, 2001·218 cites·23 claims
- 4295US12272727B2Gate-all-around integrated circuit structures having embedded GeSnB source or drain structuresINTEL CORP·Filed 2024·Granted Apr 8, 2025·2 cites·19 claims
- 4395US12107085B2Interconnect techniques for electrically connecting source/drain regions of stacked transistorsINTEL CORP·Filed 2023·Granted Oct 1, 2024·2 cites·20 claims
- 4495US10734412B2Backside contact resistance reduction for semiconductor devices with metallization on both sidesINTEL CORP·Filed 2016·Granted Aug 4, 2020·15 cites·20 claims
- 4595US10700178B2Contact resistance reduction employing germanium overlayer pre-contact metalizationINTEL CORP·Filed 2019·Granted Jun 30, 2020·7 cites·20 claims
- 4695US9397102B2III-V layers for N-type and P-type MOS source-drain contactsINTEL CORP·Filed 2015·Granted Jul 19, 2016·11 cites·21 claims
- 4795US7902009B2Graded high germanium compound films for strained semiconductor devicesINTEL CORP·Filed 2008·Granted Mar 8, 2011·425 cites·10 claims
- 4895US7821044B2Transistor with improved tip profile and method of manufacture thereofINTEL CORP·Filed 2008·Granted Oct 26, 2010·32 cites·34 claims
- 4995US7479432B2CMOS transistor junction regions formed by a CVD etching and deposition sequenceINTEL CORP·Filed 2006·Granted Jan 20, 2009·31 cites·9 claims
- 5095US7274055B2Method for improving transistor performance through reducing the salicide interface resistanceINTEL CORP·Filed 2005·Granted Sep 25, 2007·26 cites·15 claims
Showing the top 50 of 587 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →