Inventor · disambiguated record
Anthony D. Polson
Also filed as: POLSON ANTHONY D
27 granted patents·2 pending applications·242 citations·filing 2004–2012
96Inventor score
Top patents by PatentIndex Score
29 records- 0192US7089143B2Method and system for evaluating timing in an integrated circuitIBM·Filed 2004·Granted Aug 8, 2006·41 cites·19 claims
- 0289US7444608B2Method and system for evaluating timing in an integrated circuitIBM·Filed 2006·Granted Oct 28, 2008·13 cites·11 claims
- 0388US7489204B2Method and structure for chip-level testing of wire delay independent of silicon delayIBM·Filed 2005·Granted Feb 10, 2009·17 cites·20 claims
- 0486US7716616B2Slack sensitivity to parameter variation based timing analysisIBM·Filed 2007·Granted May 11, 2010·12 cites·25 claims
- 0585US7418689B2Method of generating wiring routes with matching delay in the presence of process variationIBM·Filed 2005·Granted Aug 26, 2008·12 cites·18 claims
- 0684US9310426B2On-going reliability monitoring of integrated circuit chips in the fieldIBM·Filed 2012·Granted Apr 12, 2016·6 cites·18 claims
- 0784US7302673B2Method and system for performing shapes correction of a multi-cell reticle photomask designIBM·Filed 2005·Granted Nov 27, 2007·7 cites·20 claims
- 0883US7840864B2Functional frequency testing of integrated circuitsIBM·Filed 2009·Granted Nov 23, 2010·8 cites·16 claims
- 0981US7810054B2Method of optimizing power usage of an integrated circuit design by tuning selective voltage binning cut pointIBM·Filed 2008·Granted Oct 5, 2010·11 cites·6 claims
- 1081US7401307B2Slack sensitivity to parameter variation based timing analysisIBM·Filed 2004·Granted Jul 15, 2008·24 cites·9 claims
- 1178US7877714B2System and method to optimize semiconductor power by integration of physical design timing and product performance measurementsIBM·Filed 2008·Granted Jan 25, 2011·10 cites·7 claims
- 1277US7890906B2Method of laying out integrated circuit design based on known polysilicon perimeter densities of individual cellsIBM·Filed 2008·Granted Feb 15, 2011·8 cites·16 claims
- 1376US7487487B1Design structure for monitoring cross chip delay variation on a semiconductor deviceIBM·Filed 2008·Granted Feb 3, 2009·8 cites·1 claims
- 1475US7870525B2Slack sensitivity to parameter variation based timing analysisIBM·Filed 2008·Granted Jan 11, 2011·5 cites·20 claims
- 1575US7865861B2Method of generating wiring routes with matching delay in the presence of process variationIBM·Filed 2008·Granted Jan 4, 2011·5 cites·13 claims
- 1675US7849433B2Integrated circuit with uniform polysilicon perimeter density, method and design structureIBM·Filed 2008·Granted Dec 7, 2010·7 cites·9 claims
- 1773US7823115B2Method of generating wiring routes with matching delay in the presence of process variationIBM·Filed 2008·Granted Oct 26, 2010·4 cites·2 claims
- 1873US7765351B2High bandwidth low-latency semaphore mapped protocol (SMP) for multi-core systems on chipsIBM·Filed 2007·Granted Jul 27, 2010·6 cites·20 claims
- 1971US7962874B2Method and system for evaluating timing in an integrated circuitIBM·Filed 2008·Granted Jun 14, 2011·4 cites·2 claims
- 2071US7840863B2Functional frequency testing of integrated circuitsIBM·Filed 2009·Granted Nov 23, 2010·4 cites·18 claims
- 2171US7280939B2System and method of analyzing timing effects of spatial distribution in circuitsIBM·Filed 2004·Granted Oct 9, 2007·13 cites·4 claims
- 2268US9075106B2Detecting chip alterations with light emissionBERNSTEIN KERRY·Filed 2009·Granted Jul 7, 2015·5 cites·19 claims
- 2363US7805693B2IC chip design modeling using perimeter density to electrical characteristic correlationIBM·Filed 2008·Granted Sep 28, 2010·2 cites·15 claims
- 2461US7521973B1Clock-skew tuning apparatus and methodIBM·Filed 2008·Granted Apr 21, 2009·4 cites·1 claims
- 2559US7290191B2Functional frequency testing of integrated circuitsIBM·Filed 2004·Granted Oct 30, 2007·6 cites·18 claims
- 2652US7680626B2System and method of analyzing timing effects of spatial distribution in circuitsIBM·Filed 2007·Granted Mar 16, 2010·0 cites·31 claims
- 2750US8336008B2Characterization of long range variabilityCULP JAMES A·Filed 2009·Granted Dec 18, 2012·0 cites·23 claims
- 2840US2009115447A1Design Structure for an Integrated Circuit Having State-Saving Input-Output Circuitry and a Method of Testing Such an Integrated CircuitIBM·Filed 2007·Application pending·0 cites
- 2938US2008129330A1Integrated Circuit Having State-Saving Input-Output Circuitry and a Method of Testing Such an Integrated CircuitIBM·Filed 2006·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →