Inventor · disambiguated record
Andre Schaefer
Also filed as: SCHAEFER ANDRE · SCHAEFÉR ANDRE
41 granted patents·12 pending applications·239 citations·filing 2001–2024
97Inventor score
Top patents by PatentIndex Score
53 records- 0194US8547769B2Energy efficient power distribution for 3D integrated circuit stackSARASWAT RUCHIR·Filed 2011·Granted Oct 1, 2013·75 cites·13 claims
- 0290US8037375B2Fast data eye retraining for a memoryINTEL CORP·Filed 2009·Granted Oct 11, 2011·24 cites·14 claims
- 0389US9921640B2Integrated voltage regulators with magnetically enhanced inductorsINTEL CORP·Filed 2012·Granted Mar 20, 2018·12 cites·24 claims
- 0488US8135936B2Adaptive address mapping with dynamic runtime memory mapping selectionSCHAEFER ANDRE·Filed 2009·Granted Mar 13, 2012·20 cites·19 claims
- 0587US9229466B2Fully integrated voltage regulators for multi-stack integrated circuit architecturesSARASWAT RUCHIR·Filed 2011·Granted Jan 5, 2016·11 cites·25 claims
- 0686US9135982B2Techniques for accessing a dynamic random access memory arrayINTEL CORP·Filed 2013·Granted Sep 15, 2015·11 cites·25 claims
- 0786US2024379625A1Stacked memory with interface providing offset interconnectsTAHOE RES LTD·Filed 2024·Application pending·0 cites
- 0884US9000577B2Interlayer communications for 3D integrated circuit stackDROEGE GUIDO·Filed 2011·Granted Apr 7, 2015·10 cites·14 claims
- 0983US9263422B2Interlayer communications for 3D integrated circuit stackINTEL CORP·Filed 2015·Granted Feb 16, 2016·4 cites·20 claims
- 1081US9230614B2Separate microchannel voltage domains in stacked memory architectureSCHAEFER ANDRE·Filed 2011·Granted Jan 5, 2016·6 cites·24 claims
- 1180US9026767B2Adaptive address mapping with dynamic runtime memory mapping selectionSCHAEFER ANDRE·Filed 2012·Granted May 5, 2015·6 cites·21 claims
- 1280US8811110B2Configuration for power reduction in DRAMSCHAEFER ANDRE·Filed 2012·Granted Aug 19, 2014·6 cites·9 claims
- 1377US9391453B2Power management in multi-die assembliesINTEL CORP·Filed 2013·Granted Jul 12, 2016·4 cites·29 claims
- 1474US10079489B2Power management in multi-die assembliesINTEL CORP·Filed 2016·Granted Sep 18, 2018·2 cites·19 claims
- 1573US9911689B2Through-body-via isolated coaxial capacitor and techniques for forming sameINTEL CORP·Filed 2013·Granted Mar 6, 2018·3 cites·7 claims
- 1666US9086881B2Mechanism for facilitating write tracking for following data eye movements across changing thermal conditions in memory systemsLIU TSUN HO·Filed 2012·Granted Jul 21, 2015·4 cites·24 claims
- 1766US7321240B2Driver circuit for binary signalsINFINEON TECHNOLOGIES AG·Filed 2005·Granted Jan 22, 2008·5 cites·13 claims
- 1864US8971087B2Stacked memory with interface providing offset interconnectsVOGT PETE·Filed 2011·Granted Mar 3, 2015·1 cites·21 claims
- 1963US12046577B2Stacked memory with interface providing offset interconnectsTAHOE RES LTD·Filed 2019·Granted Jul 23, 2024·0 cites·20 claims
- 2061US10853216B2Mechanism for facilitating write tracking for following data eye movements across changing thermal conditions in memory systemsINTEL CORP·Filed 2015·Granted Dec 1, 2020·1 cites·13 claims
- 2161US6625065B2Method for masking DQ bitsINFINEON TECHNOLOGIES AG·Filed 2001·Granted Sep 23, 2003·11 cites·6 claims
- 2259US9768148B2Stacked memory with interface providing offset interconnectsINTEL CORP·Filed 2014·Granted Sep 19, 2017·0 cites·24 claims
- 2358US9287196B2Resonant clocking for three-dimensional stacked devicesINTEL CORP·Filed 2012·Granted Mar 15, 2016·1 cites·14 claims
- 2458US8321719B2Efficient clocking scheme for a bidirectional data linkSCHAEFER ANDRE·Filed 2009·Granted Nov 27, 2012·1 cites·15 claims
- 2558US7355921B2Device in a memory circuit for definition of waiting timesINFINEON TECHNOLOGIES AG·Filed 2006·Granted Apr 8, 2008·0 cites·20 claims
- 2657US9361970B2Configuration for power reduction in DRAMINTEL CORP·Filed 2014·Granted Jun 7, 2016·1 cites·11 claims
- 2757US2018122779A1STACKED MEMORY WITH INTERFACE PROVIDING OFFSET Interconnect SINTEL CORP·Filed 2017·Application pending·0 cites
- 2856US2022340752A1Thermoplastic molding compositionBASF SE·Filed 2020·Application pending·0 cites
- 2955US9311983B2Dynamically applying refresh overcharge voltage to extend refresh cycle timeSCHAEFER ANDRE·Filed 2014·Granted Apr 12, 2016·1 cites·20 claims
- 3052US12017270B2Three-plate pressure die casting mold having improved sprue separation, and method for pressure die castingBAYERISCHE MOTOREN WERKE AG·Filed 2021·Granted Jun 25, 2024·0 cites·10 claims
- 3152US6917562B2Semi-conductor component with clock relaying deviceINFINEON TECHNOLOGIES AG·Filed 2003·Granted Jul 12, 2005·7 cites·20 claims
- 3252US2024294753A1Mixture of Semi-Aromatic Polyamides and Molded Articles with Improved Weld Line StrengthBASF SE·Filed 2020·Application pending·0 cites
- 3351US11964323B2Three-plate pressure die casting mold having improved sprue separation, and method for pressure die casting (II)BAYERISCHE MOTOREN WERKE AG·Filed 2021·Granted Apr 23, 2024·0 cites·10 claims
- 3447US6690612B2Voltage supply for semiconductor memoryINFINEON TECHNOLOGIES AG·Filed 2001·Granted Feb 10, 2004·5 cites·5 claims
- 3545US6911732B2Integrated circuitINFINEON TECHNOLOGIES AG·Filed 2002·Granted Jun 28, 2005·1 cites·21 claims
- 3645US6783596B2Wafer handling deviceINFINEON TECHNOLOGIES AG·Filed 2002·Granted Aug 31, 2004·3 cites·4 claims
- 3744US7180805B2Differental current source for generating DRAM refresh signalINFINEON TECHNOLOGIES AG·Filed 2003·Granted Feb 20, 2007·3 cites·14 claims
- 3844US2016306566A1Data reorder during memory accessLU SHIH-LIEN L·Filed 2013·Application pending·0 cites
- 3941US12121959B2Three-plate die casting mold having a sprue system and improved sprue separation, and die casting methodBAYERISCHE MOTOREN WERKE AG·Filed 2021·Granted Oct 22, 2024·0 cites·8 claims
- 4040US8959271B2System and method for accessing memoryINTEL CORP·Filed 2013·Granted Feb 17, 2015·0 cites·18 claims
- 4140US2006049511A1Integrated semiconductor circuit and method for producing an integrated semiconductor circuitSCHAEFER ANDRE·Filed 2005·Application pending·0 cites
- 4239US9472249B2Techniques for accessing a dynamic random access memory arrayINTEL CORP·Filed 2015·Granted Oct 18, 2016·0 cites·25 claims
- 4339US9087559B2Memory sense amplifier voltage modulationINTEL CORP·Filed 2012·Granted Jul 21, 2015·0 cites·25 claims
- 4439US2024092430A1Rear Structure for a Motor Vehicle and Motor Vehicle Comprising Such a Rear StructureBAYERISCHE MOTOREN WERKE AG·Filed 2022·Application pending·0 cites
- 4537US10851516B2Shaft cover for shafts, channel entrances, or drainage channelsBASF SE·Filed 2017·Granted Dec 1, 2020·0 cites·9 claims
- 4637US7587655B2Method of transferring signals between a memory device and a memory controllerINFINEON TECHNOLOGIES AG·Filed 2005·Granted Sep 8, 2009·0 cites·19 claims
- 4733US2006152957A1Circuit arrangement and method for setting operating parameters in a RAM moduleSCHAEFER ANDRE·Filed 2005·Application pending·0 cites
- 4833US2006085705A1Memory circuit comprising an initialization unit, and method for optimizing data reception parameters in a memory controllerSCHAEFER ANDRE·Filed 2005·Application pending·0 cites
- 4932US2002196868A1Evaluation device for assessing a digital data signal, in particular a data signal for a semiconductor memory circuitFiled 2002·Application pending·0 cites
- 5029US7049930B2Arrangement of several resistors jointly positioned in a well of a semiconductor device, and a semiconductor device including at least one such arrangementINFINEON TECHNOLOGIES AG·Filed 2003·Granted May 23, 2006·0 cites·22 claims
Showing the top 50 of 53 patent records by PatentIndex Score.
Join the waitlist — get patent alerts
Get an alert when Andre Schaefer files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →