Inventor · disambiguated record
Andrey P. Sokolov
Also filed as: SOKOLOV ANDREY P · SOKOLOV ANDREY PAVLOVICH
16 granted patents·4 pending applications·34 citations·filing 2009–2014
88Inventor score
Top patents by PatentIndex Score
20 records- 0184US9337866B2Apparatus for processing signals carrying modulation-encoded parity bitsLSI CORP·Filed 2013·Granted May 10, 2016·9 cites·20 claims
- 0281US8850437B2Two-pass linear complexity task schedulerSHUTKIN YURII S·Filed 2011·Granted Sep 30, 2014·8 cites·18 claims
- 0374US8397143B2BCH or reed-solomon decoder with syndrome modificationNEZNANOV ILYA V·Filed 2009·Granted Mar 12, 2013·10 cites·20 claims
- 0464US8656206B2Timer manager architecture based on binary heapGASANOV ELYAR E·Filed 2011·Granted Feb 18, 2014·2 cites·22 claims
- 0561US8365054B2Soft reed-solomon decoder based on error-and-erasure reed-solomon decoderLSI CORP·Filed 2009·Granted Jan 29, 2013·4 cites·20 claims
- 0650US8621329B2Reconfigurable BCH decoderPANTELEEV PAVEL A·Filed 2011·Granted Dec 31, 2013·1 cites·20 claims
- 0744US2014223267A1Radix-4 viterbi forward error correction decodingLSI CORP·Filed 2014·Application pending·0 cites
- 0843US8923413B2Optimization of data processors with irregular patternsLSI CORP·Filed 2012·Granted Dec 30, 2014·0 cites·17 claims
- 0943US8868890B2No-delay microsequencerSHUTKIN YURII S·Filed 2011·Granted Oct 21, 2014·0 cites·20 claims
- 1042US9319181B2Parallel decoder for multiple wireless standardsSOKOLOV ANDREY P·Filed 2011·Granted Apr 19, 2016·0 cites·20 claims
- 1142US8923315B2Packet router having a hierarchical buffer structureLSI CORP·Filed 2013·Granted Dec 30, 2014·0 cites·14 claims
- 1238US8775914B2Radix-4 viterbi forward error correction decodingGASANOV ELYAR E·Filed 2011·Granted Jul 8, 2014·0 cites·18 claims
- 1338US8775893B2Variable parity encoderPANTELEEV PAVEL A·Filed 2012·Granted Jul 8, 2014·0 cites·18 claims
- 1438US8700969B2Reconfigurable encoding per multiple communications standardsPANTELEEV PAVEL A·Filed 2011·Granted Apr 15, 2014·0 cites·20 claims
- 1537US8699396B2Branch metrics calculation for multiple communications standardsPANTELEEV PAVEL A·Filed 2011·Granted Apr 15, 2014·0 cites·20 claims
- 1636US2014040342A1High speed add-compare-select circuitLSI CORP·Filed 2013·Application pending·0 cites
- 1736US2014164876A1Modulation coding of parity bits generated using an error-correction codeLSI CORP·Filed 2013·Application pending·0 cites
- 1835US2012166501A1Computation of jacobian logarithm operationSOKOLOV ANDREY P·Filed 2011·Application pending·0 cites
- 1934US8938654B2Programmable circuit for high speed computation of the interleaver tables for multiple wireless standardsSOKOLOV ANDREY P·Filed 2010·Granted Jan 20, 2015·0 cites·20 claims
- 2034US8842784B2L-value generation in a decoderSOKOLOV ANDREY P·Filed 2011·Granted Sep 23, 2014·0 cites·18 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →