Inventor · disambiguated record
Arkady Bramnik
Also filed as: BRAMNIK ARKADY
8 granted patents·2 pending applications·45 citations·filing 1996–2022
81Inventor score
Top patents by PatentIndex Score
10 records- 0186US10725788B1Advanced error detection for integer single instruction, multiple data (SIMD) arithmetic operationsINTEL CORP·Filed 2019·Granted Jul 28, 2020·5 cites·21 claims
- 0286US10346171B2End-to end transmission of redundant bits for physical storage location identifiers between first and second register rename storage structuresINTEL CORP·Filed 2017·Granted Jul 9, 2019·6 cites·23 claims
- 0372US10819343B2Flip-flop with soft error toleranceINTEL CORP·Filed 2019·Granted Oct 27, 2020·2 cites·24 claims
- 0468US5668766AMethod and apparatus for increasing memory read access speed using double-sensingINTEL CORP·Filed 1996·Granted Sep 16, 1997·32 cites·10 claims
- 0561US11106271B2System, apparatus and method for dynamically controlling error protection features of a processorINTEL CORP·Filed 2019·Granted Aug 31, 2021·0 cites·20 claims
- 0655US10437315B2System, apparatus and method for dynamically controlling error protection features of a processorINTEL CORP·Filed 2017·Granted Oct 8, 2019·0 cites·17 claims
- 0747US8826107B2Efficient cache search and error detectionGENDLER ALEXANDER·Filed 2012·Granted Sep 2, 2014·0 cites·20 claims
- 0846US10133620B2Detecting errors in register renaming by comparing value representing complete error free set of identifiers and value representing identifiers in register rename unitINTEL CORP·Filed 2017·Granted Nov 20, 2018·0 cites·25 claims
- 0943US2023273811A1Reducing silent data errors using a hardware micro-lockstep techniqueINTEL CORP·Filed 2022·Application pending·0 cites
- 1028US2012079349A1Method and apparatus for multi-bit upset protectionBRAMNIK ARKADY·Filed 2010·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →