Inventor · disambiguated record
Arun Gunda
Also filed as: GUNDA ARUN · GUNDA ARUN K
12 granted patents·2 pending applications·234 citations·filing 1995–2022
91Inventor score
Top patents by PatentIndex Score
14 records- 0191US7831876B2Testing a circuit with compressed scan chain subsetsLSI CORP·Filed 2007·Granted Nov 9, 2010·25 cites·11 claims
- 0289US7555688B2Method for implementing test generation for systematic scan reconfiguration in an integrated circuitLSI LOGIC CORP·Filed 2005·Granted Jun 30, 2009·24 cites·16 claims
- 0388US5663967ADefect isolation using scan-path testing and electron beam probing in multi-level high density asicsLSI LOGIC CORP·Filed 1995·Granted Sep 2, 1997·99 cites·4 claims
- 0487US8627160B2System and device for reducing instantaneous voltage droop during a scan shift operationDEVTA-PRASANNA NARENDRA·Filed 2010·Granted Jan 7, 2014·13 cites·18 claims
- 0581US7461307B2System and method for improving transition delay fault coverage in delay fault tests through use of an enhanced scan flip-flopLSI CORP·Filed 2005·Granted Dec 2, 2008·12 cites·20 claims
- 0675US7293210B2System and method for improving transition delay fault coverage in delay fault tests through use of transition launch flip-flopLSI CORP·Filed 2005·Granted Nov 6, 2007·8 cites·22 claims
- 0767US6449751B1Method of analyzing static current test vectors with reduced file sizes for semiconductor integrated circuitsLSI LOGIC CORP·Filed 2001·Granted Sep 10, 2002·17 cites·22 claims
- 0860US8418008B2Test technique to apply a variable scan clock including a scan clock modifier on an integrated circuitCHAKRAVARTY SREEJIT·Filed 2008·Granted Apr 9, 2013·4 cites·22 claims
- 0959US5903578ATest shells for protecting proprietary information in asic coresLSI LOGIC CORP·Filed 1996·Granted May 11, 1999·23 cites·8 claims
- 1054US7461315B2Method and system for improving quality of a circuit through non-functional test pattern identificationLSI CORP·Filed 2005·Granted Dec 2, 2008·2 cites·18 claims
- 1149US12405157B2Optical fiber-based hydrophoneOPTICS11 B V·Filed 2022·Granted Sep 2, 2025·0 cites·30 claims
- 1236US2006136795A1Method of testing scan chain integrity and tester setup for scan block testingLSI LOGIC CORP·Filed 2004·Application pending·0 cites
- 1333US6212655B1IDDQ test solution for large asicsLSI LOGIC CORP·Filed 1997·Granted Apr 3, 2001·7 cites·7 claims
- 1429US2005091622A1Method of grouping scan flops based on clock domains for scan testingFiled 2003·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →