Inventor · disambiguated record
Arghya Sain
Also filed as: SAIN ARGHYA
4 granted patents·10 pending applications·3 citations·filing 2017–2023
60Inventor score
Technology areasH10W
Top patents by PatentIndex Score
14 records- 0177US11869842B2Scalable high speed high bandwidth IO signaling package architecture and method of makingINTEL CORP·Filed 2019·Granted Jan 9, 2024·2 cites·17 claims
- 0269US2024088047A1Scalable high speed high bandwidth io signaling package architecture and method of makingINTEL CORP·Filed 2023·Application pending·0 cites
- 0366US10475736B2Via architecture for increased density interfaceINTEL CORP·Filed 2017·Granted Nov 12, 2019·1 cites·24 claims
- 0451US2024006286A1Layer selection for routing high-speed signals in substratesINTEL CORP·Filed 2022·Application pending·0 cites
- 0550US12057413B2Package design scheme for enabling high-speed low-loss signaling and mitigation of manufacturing risk and costINTEL CORP·Filed 2019·Granted Aug 6, 2024·0 cites·21 claims
- 0650US2023299044A1Passive electrical components in mold metal layers of a multi-die complexINTEL CORP·Filed 2022·Application pending·0 cites
- 0749US2023197646A1Low loss microstrip and stripline routing with blind trench vias for high speed signaling on a glass coreINTEL CORP·Filed 2021·Application pending·0 cites
- 0848US2023097236A1Substrate layer count reduction enabled with bump pitch scale through glass core via pitchINTEL CORP·Filed 2021·Application pending·0 cites
- 0948US2023207406A1Ultra low loss and high-density routing between coresINTEL CORP·Filed 2021·Application pending·0 cites
- 1048US2023207405A1Ultra low loss routing between glass coresINTEL CORP·Filed 2021·Application pending·0 cites
- 1147US2023197593A1Coupled fins with blind trench structuresINTEL CORP·Filed 2021·Application pending·0 cites
- 1246US2023207494A1Single layer and multilayer magnetic inductors between substrate coresXIE JIANYONG·Filed 2021·Application pending·0 cites
- 1342US11705390B2Variable in-plane signal to ground reference configurationsINTEL CORP·Filed 2019·Granted Jul 18, 2023·0 cites·20 claims
- 1440US2021296241A1Microelectronic package with reduced through-substrate routingINTEL CORP·Filed 2020·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →