Inventor · disambiguated record
Arun Vaidyanath
Also filed as: VAIDYANATH ARUN
11 granted patents·1 pending application·39 citations·filing 2010–2024
86Inventor score
Top patents by PatentIndex Score
12 records- 0194US9298228B1Memory capacity expansion using a memory riserRAMBUS INC·Filed 2015·Granted Mar 29, 2016·28 cites·17 claims
- 0285US9183166B2Expandable asymmetric-channel memory systemSHAEFFER IAN·Filed 2010·Granted Nov 10, 2015·6 cites·23 claims
- 0385US2025156348A1Asymmetric-channel memory systemRAMBUS INC·Filed 2024·Application pending·0 cites
- 0476US9996485B2Asymmetric-channel memory systemRAMBUS INC·Filed 2017·Granted Jun 12, 2018·1 cites·20 claims
- 0575US12189548B2Buffer IC with asymmetric memory module interfacesRAMBUS INC·Filed 2021·Granted Jan 7, 2025·0 cites·20 claims
- 0669US11200181B2Asymmetric-channel memory systemRAMBUS INC·Filed 2020·Granted Dec 14, 2021·0 cites·20 claims
- 0763US10621120B2Buffer component for asymmetric-channel memory systemRAMBUS INC·Filed 2018·Granted Apr 14, 2020·0 cites·20 claims
- 0861US8762657B2Method and system for synchronizing address and control signals in threaded memory modulesVAIDYANATH ARUN·Filed 2010·Granted Jun 24, 2014·3 cites·30 claims
- 0959US9632956B2Expandable asymmetric-channel memory systemRAMBUS INC·Filed 2015·Granted Apr 25, 2017·0 cites·20 claims
- 1049US9036436B2Supporting calibration for sub-rate operation in clocked memory systemsBANSAL AKASH·Filed 2012·Granted May 19, 2015·1 cites·20 claims
- 1146US9507738B2Method and system for synchronizing address and control signals in threaded memory modulesRAMBUS INC·Filed 2014·Granted Nov 29, 2016·0 cites·23 claims
- 1243US9349422B2Supporting calibration for sub-rate operation in clocked memory systemsRAMBUS INC·Filed 2015·Granted May 24, 2016·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →