Inventor · disambiguated record
Arch Zaliznyak
Also filed as: ZALIZNYAK ARCH
18 granted patents·3 pending applications·298 citations·filing 1997–2024
94Inventor score
Top patents by PatentIndex Score
21 records- 0189US8571059B1Apparatus and methods for serial interfaces with shared datapathsZALIZNYAK ARCH·Filed 2011·Granted Oct 29, 2013·17 cites·18 claims
- 0289US6218858B1Programmable input/output circuit for FPGA for use in TTL, GTL, GTLP, LVPECL and LVDS circuitsXILINX INC·Filed 1999·Granted Apr 17, 2001·75 cites·5 claims
- 0385US7848318B2Serializer circuitry for high-speed serial data transmitters on programmable logic device integrated circuitsALTERA CORP·Filed 2006·Granted Dec 7, 2010·11 cites·13 claims
- 0484US8700825B1Heterogeneous high-speed serial interface system with phase-locked loop architecture and clock distribution systemALTERA CORP·Filed 2012·Granted Apr 15, 2014·6 cites·25 claims
- 0584US8570197B2Serializer circuitry for high-speed serial data transmitters on programmable logic device integrated circuitsNGUYEN TOAN THANH·Filed 2010·Granted Oct 29, 2013·6 cites·7 claims
- 0684US6246259B1High-speed programmable logic architecture having active CMOS device driversXILINX INC·Filed 1998·Granted Jun 12, 2001·68 cites·3 claims
- 0782US6130550AScaleable padframe interface circuit for FPGA yielding improved routability and faster chip layoutDYNALOGIC·Filed 1997·Granted Oct 10, 2000·47 cites·15 claims
- 0877US7343569B1Apparatus and method for reset distributionALTERA CORP·Filed 2006·Granted Mar 11, 2008·7 cites·26 claims
- 0976US8581653B1Techniques for providing clock signals in clock networksMARURI VICTOR·Filed 2011·Granted Nov 12, 2013·6 cites·20 claims
- 1072US8994425B2Techniques for aligning and reducing skew in serial data signalsVENKATA RAMANAND·Filed 2012·Granted Mar 31, 2015·3 cites·21 claims
- 1171US7028270B1Apparatus and method for reset distributionALTERA CORP·Filed 2003·Granted Apr 11, 2006·14 cites·35 claims
- 1265US6985021B1Circuits and techniques for conditioning differential signalsALTERA CORP·Filed 2003·Granted Jan 10, 2006·13 cites·33 claims
- 1364US7659838B2Deserializer circuitry for high-speed serial data receivers on programmable logic device integrated circuitsALTERA CORP·Filed 2006·Granted Feb 9, 2010·5 cites·18 claims
- 1461US9077330B2Serializer circuitry for high-speed serial data transmitters on programmable logic device integrated circuitsALTERA CORP·Filed 2013·Granted Jul 7, 2015·1 cites·20 claims
- 1557US2024213985A1Systems And Methods For Configuring Signal Paths In An Interposer Between Integrated CircuitsALTERA CORP·Filed 2024·Application pending·0 cites
- 1653US2024162189A1Active Interposers For Migration Of PackagesALTERA CORP·Filed 2023·Application pending·0 cites
- 1750US8812755B2Heterogeneous high-speed serial interface system with phase-locked loop architecture and clock distribution systemALTERA CORP·Filed 2014·Granted Aug 19, 2014·0 cites·20 claims
- 1847US8098087B1Method and apparatus for standby voltage offset cancellationLAM JOHN DUNG-NGOC·Filed 2007·Granted Jan 17, 2012·2 cites·18 claims
- 1943US8835769B1High speed serial interfaceZALIZNYAK ARCH·Filed 2012·Granted Sep 16, 2014·0 cites·18 claims
- 2043US6232818B1Voltage translatorXILINX INC·Filed 1998·Granted May 15, 2001·17 cites·11 claims
- 2140US2022115047A1Circuits And Methods For Sub-Bank Sharing Of External InterfacesINTEL CORP·Filed 2021·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →