Inventor · disambiguated record
Arno Zechmann
Also filed as: ZECHMANN ARNO
5 granted patents·3 pending applications·62 citations·filing 2012–2019
77Inventor score
Top patents by PatentIndex Score
8 records- 0194US9660037B1Semiconductor wafer and methodINFINEON TECHNOLOGIES AUSTRIA AG·Filed 2015·Granted May 23, 2017·39 cites·19 claims
- 0288US8502274B1Integrated circuit including power transistor cells and a connecting lineMATOY KURT·Filed 2012·Granted Aug 6, 2013·18 cites·25 claims
- 0385US10256149B2Semiconductor wafer dicing crack prevention using chip peripheral trenchesINFINEON TECHNOLOGIES AUSTRIA AG·Filed 2017·Granted Apr 9, 2019·5 cites·16 claims
- 0454US10903120B2Semiconductor wafer dicing crack prevention using chip peripheral trenchesINFINEON TECHNOLOGIES AUSTRIA AG·Filed 2018·Granted Jan 26, 2021·0 cites·13 claims
- 0553US2019259874A1Wafer based beol process for chip embeddingINFINEON TECHNOLOGIES AG·Filed 2019·Application pending·0 cites
- 0650US9425090B2Method of electrodepositing gold on a copper seed layer to form a gold metallization structureINFINEON TECHNOLOGIES AUSTRIA AG·Filed 2014·Granted Aug 23, 2016·0 cites·14 claims
- 0748US2015221764A1Wafer based beol process for chip embeddingINFINEON TECHNOLOGIES AG·Filed 2014·Application pending·0 cites
- 0843US2016336272A1Semiconductor Device Having Gold Metallization StructuresINFINEON TECHNOLOGIES AUSTRIA AG·Filed 2016·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →