Inventor · disambiguated record
Ashish Darbari
Also filed as: DARBARI ASHISH
41 granted patents·5 pending applications·39 citations·filing 2015–2025
96Inventor score
Files withIMAGINATION TECH LTD46
Top patents by PatentIndex Score
46 records- 0190US10331831B2Assessing performance of a hardware design using formal evaluation logicIMAGINATION TECH LTD·Filed 2016·Granted Jun 25, 2019·5 cites·19 claims
- 0290US9563727B2Clock verificationIMAGINATION TECH LTD·Filed 2015·Granted Feb 7, 2017·6 cites·18 claims
- 0388US10346571B2Livelock detection in a hardware design using formal evaluation logicIMAGINATION TECH LTD·Filed 2016·Granted Jul 9, 2019·4 cites·18 claims
- 0488US9767236B2Deadlock detection in hardware design using assertion based verificationIMAGINATION TECH LTD·Filed 2015·Granted Sep 19, 2017·8 cites·19 claims
- 0587US11467840B2Livelock recovery circuit for detecting illegal repetition of an instruction and transitioning to a known stateIMAGINATION TECH LTD·Filed 2020·Granted Oct 11, 2022·2 cites·19 claims
- 0687US10366187B2Clock verificationIMAGINATION TECH LTD·Filed 2017·Granted Jul 30, 2019·4 cites·19 claims
- 0785US2025111115A1Assessing performance of a hardware design using formal evaluation logicIMAGINATION TECH LTD·Filed 2024·Application pending·0 cites
- 0884US2024411972A1Detecting out-of-bounds violations in a hardware design using formal verificationIMAGINATION TECH LTD·Filed 2024·Application pending·0 cites
- 0983US11030039B2Out-of-bounds recovery circuitIMAGINATION TECH LTD·Filed 2020·Granted Jun 8, 2021·1 cites·20 claims
- 1083US2024330553A1Livelock detection in a hardware design using formal evaluation logicIMAGINATION TECH LTD·Filed 2024·Application pending·0 cites
- 1182US10936775B2Detecting out-of-bounds violations in a hardware design using formal verificationIMAGINATION TECH LTD·Filed 2020·Granted Mar 2, 2021·1 cites·20 claims
- 1281US12093621B2Detecting out-of-bounds violations in a hardware design using formal verificationIMAGINATION TECH LTD·Filed 2023·Granted Sep 17, 2024·0 cites·20 claims
- 1380US10552155B2Livelock recovery circuit configured to detect illegal repetition of an instruction and transition to a known stateIMAGINATION TECH LTD·Filed 2016·Granted Feb 4, 2020·2 cites·18 claims
- 1479US12271259B2Out-of-bounds recovery circuitIMAGINATION TECH LTD·Filed 2023·Granted Apr 8, 2025·0 cites·20 claims
- 1579US11250927B2Formal verification tool to verify hardware design of memory unitIMAGINATION TECH LTD·Filed 2020·Granted Feb 15, 2022·1 cites·20 claims
- 1679US10963611B2Assessing performance of a hardware design using formal evaluation logicIMAGINATION TECH LTD·Filed 2019·Granted Mar 30, 2021·1 cites·11 claims
- 1778US12175179B2Assessing performance of a hardware design using formal evaluation logicIMAGINATION TECH LTD·Filed 2022·Granted Dec 24, 2024·0 cites·19 claims
- 1878US2024311487A1Verifying firmware binary images using a hardware design and formal assertionsIMAGINATION TECH LTD·Filed 2024·Application pending·0 cites
- 1977US2025156267A1Out-of-Bounds Recovery CircuitIMAGINATION TECH LTD·Filed 2025·Application pending·0 cites
- 2076US12050849B2Livelock detection in a hardware design using formal evaluation logicIMAGINATION TECH LTD·Filed 2022·Granted Jul 30, 2024·0 cites·9 claims
- 2176US10817367B2Out-of-bounds recovery circuitIMAGINATION TECH LTD·Filed 2017·Granted Oct 27, 2020·1 cites·17 claims
- 2275US11663386B2Detecting out-of-bounds violations in a hardware design using formal verificationIMAGINATION TECH LTD·Filed 2022·Granted May 30, 2023·0 cites·20 claims
- 2374US11847456B2Livelock recovery circuit for detecting illegal repetition of an instruction and transitioning to a known stateIMAGINATION TECH LTD·Filed 2022·Granted Dec 19, 2023·0 cites·20 claims
- 2473US11593193B2Out-of-bounds recovery circuitIMAGINATION TECH LTD·Filed 2021·Granted Feb 28, 2023·0 cites·20 claims
- 2572US11250192B2Detecting out-of-bounds violations in a hardware design using formal verificationIMAGINATION TECH LTD·Filed 2021·Granted Feb 15, 2022·0 cites·20 claims
- 2672US10580511B2Hardware monitor to verify memory unitsIMAGINATION TECH LTD·Filed 2016·Granted Mar 3, 2020·1 cites·19 claims
- 2771US11531799B2Assessing performance of a hardware design using formal evaluation logicIMAGINATION TECH LTD·Filed 2021·Granted Dec 20, 2022·0 cites·19 claims
- 2871US11373025B2Livelock detection in a hardware design using formal evaluation logicIMAGINATION TECH LTD·Filed 2020·Granted Jun 28, 2022·0 cites·11 claims
- 2970US10083262B2Deadlock detection in hardware design using assertion based verificationIMAGINATION TECH LTD·Filed 2017·Granted Sep 25, 2018·1 cites·20 claims
- 3069US11989299B2Verifying firmware binary images using a hardware design and formal assertionsIMAGINATION TECH LTD·Filed 2021·Granted May 21, 2024·0 cites·14 claims
- 3169US11948652B2Formal verification tool to verify hardware design of memory unitIMAGINATION TECH LTD·Filed 2022·Granted Apr 2, 2024·0 cites·20 claims
- 3269US11475193B2Control path verification of hardware design for pipelined processIMAGINATION TECH LTD·Filed 2021·Granted Oct 18, 2022·0 cites·20 claims
- 3368US9767057B2Hardware data structure for tracking partially ordered and reordered transactionsIMAGINATION TECH LTD·Filed 2015·Granted Sep 19, 2017·1 cites·20 claims
- 3466US10909289B2Livelock detection in a hardware design using formal evaluation logicIMAGINATION TECH LTD·Filed 2019·Granted Feb 2, 2021·0 cites·18 claims
- 3564US10949590B2Control path verification of hardware design for pipelined processIMAGINATION TECH LTD·Filed 2019·Granted Mar 16, 2021·0 cites·20 claims
- 3664US10929583B2Clock verificationIMAGINATION TECH LTD·Filed 2019·Granted Feb 23, 2021·0 cites·20 claims
- 3762US10755011B2Detecting out-of-bounds violations in a hardware design using formal verificationIMAGINATION TECH LTD·Filed 2017·Granted Aug 25, 2020·0 cites·17 claims
- 3859US11010477B2Verifying firmware binary images using a hardware design and formal assertionsIMAGINATION TECH LTD·Filed 2017·Granted May 18, 2021·0 cites·18 claims
- 3958US10067896B2Hardware data structure for tracking partially ordered and reordered transactionsIMAGINATION TECH LTD·Filed 2017·Granted Sep 4, 2018·0 cites·20 claims
- 4055US10325044B2Control path verification of hardware design for pipelined processIMAGINATION TECH LTD·Filed 2016·Granted Jun 18, 2019·0 cites·18 claims
- 4155US10089138B2Hardware data structure for tracking ordered transactionsIMAGINATION TECH LTD·Filed 2016·Granted Oct 2, 2018·0 cites·20 claims
- 4253US9519611B2Hardware data structure for tracking ordered transactionsIMAGINATION TECH LTD·Filed 2015·Granted Dec 13, 2016·0 cites·20 claims
- 4350US10210119B2Arbiter verificationIMAGINATION TECH LTD·Filed 2017·Granted Feb 19, 2019·0 cites·20 claims
- 4449US9626465B2Arbiter verificationIMAGINATION TECH LTD·Filed 2015·Granted Apr 18, 2017·0 cites·17 claims
- 4546US10108768B2Identifying bugs in a counter using formalIMAGINATION TECH LTD·Filed 2016·Granted Oct 23, 2018·0 cites·17 claims
- 4640US10359825B2Dynamic power measurement using formalIMAGINATION TECH LTD·Filed 2016·Granted Jul 23, 2019·0 cites·16 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →