Inventor · disambiguated record
Asher Hazanchuk
Also filed as: HAZANCHUK ASHER
12 granted patents·9 pending applications·522 citations·filing 1993–2025
91Inventor score
Top patents by PatentIndex Score
21 records- 0198US6943579B1Variable fixed multipliers using memory blocksALTERA CORP·Filed 2003·Granted Sep 13, 2005·418 cites·39 claims
- 0284US9535705B1Flexible hardware programmable scalable parallel processorHAZANCHUK ASHER·Filed 2014·Granted Jan 3, 2017·9 cites·10 claims
- 0383US7356554B1Variable fixed multipliers using memory blocksALTERA CORP·Filed 2005·Granted Apr 8, 2008·14 cites·37 claims
- 0481US6888372B1Programmable logic device with soft multiplierALTERA CORP·Filed 2002·Granted May 3, 2005·28 cites·27 claims
- 0573US8977885B1Programmable logic device data rate booster for digital signal processingHAZANCHUK ASHER·Filed 2012·Granted Mar 10, 2015·4 cites·19 claims
- 0671US2023316059A1Neural networks processing units redundancy removalNEURONIX AI LABS INC·Filed 2023·Application pending·0 cites
- 0769US7348914B1Method and systems to align outputs signals of an analog-to-digital converterLATTICE SEMICONDUCTOR CORP·Filed 2006·Granted Mar 25, 2008·8 cites·18 claims
- 0869US2025181905A1Neural networks processing units performance optimizationNEURONIX AI LABS INC·Filed 2025·Application pending·0 cites
- 0967US5537564ATechnique for accessing and refreshing memory locations within electronic storage devices which need to be refreshed with minimum power consumptionZILOG INC·Filed 1993·Granted Jul 16, 1996·34 cites·14 claims
- 1060US2023394278A1Neural networks processing units foldingNEURONIX AI LABS INC·Filed 2023·Application pending·0 cites
- 1160US2023368001A1Neural networks processing units pairing, symmetry, and stop-on-minusNEURONIX AI LABS INC·Filed 2023·Application pending·0 cites
- 1259US2023306235A1Neural networks processing units performance optimization parallel modeNEURONIX AI LABS INC·Filed 2023·Application pending·0 cites
- 1359US2023306243A1Neural networks processing units weight sparsity removalNEURONIX AI LABS INC·Filed 2023·Application pending·0 cites
- 1459US2023325648A1Neural networks processing units activation sparsity removalNEURONIX AI LABS INC·Filed 2023·Application pending·0 cites
- 1554US2022188611A1Neural networks processing units performance optimizationNEURONIX AI LABS INC·Filed 2021·Application pending·0 cites
- 1653US8463832B1Digital signal processing block architecture for programmable logic deviceHAZANCHUK ASHER·Filed 2008·Granted Jun 11, 2013·3 cites·10 claims
- 1752US7058675B1Apparatus and method for implementing efficient arithmetic circuits in programmable logic devicesALTERA CORP·Filed 2001·Granted Jun 6, 2006·2 cites·18 claims
- 1850US7124161B2Apparatus and method for implementing efficient arithmetic circuits in programmable logic devicesALTERA CORP·Filed 2005·Granted Oct 17, 2006·1 cites·10 claims
- 1949US7987222B1Method and apparatus for implementing a multiplier utilizing digital signal processor block memory extensionALTERA CORP·Filed 2004·Granted Jul 26, 2011·1 cites·18 claims
- 2041US7688919B1Parallel samples, parallel coefficients, time division multiplexing correlator architectureALTERA CORP·Filed 2001·Granted Mar 30, 2010·0 cites·45 claims
- 2141US2006277240A1Apparatus and method for implementing efficient arithmetic circuits in programmable logic devicesCHOO CHANG·Filed 2006·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →