Inventor · disambiguated record
Ashok Jagannathan
Also filed as: JAGANNATHAN ASHOK
10 granted patents·2 pending applications·31 citations·filing 2011–2023
84Inventor score
Top patents by PatentIndex Score
12 records- 0189US11263143B2Coherent accelerator fabric controllerINTEL CORP·Filed 2017·Granted Mar 1, 2022·5 cites·25 claims
- 0284US9430392B2Supporting large pages in hardware prefetchersJAIN PRABHAT·Filed 2014·Granted Aug 30, 2016·14 cites·20 claims
- 0381US12197374B2Peer-to-peer link sharing for upstream communications from XPUS to a host processorINTEL CORP·Filed 2021·Granted Jan 14, 2025·1 cites·20 claims
- 0476US8862828B2Sub-numa clusteringSARAF RAVINDRA P·Filed 2012·Granted Oct 14, 2014·8 cites·32 claims
- 0576US2024118892A1Apparatuses, methods, and systems for neural networksINTEL CORP·Filed 2023·Application pending·0 cites
- 0667US11663135B2Bias-based coherency in an interconnect fabricINTEL CORP·Filed 2021·Granted May 30, 2023·0 cites·20 claims
- 0767US2022050683A1Apparatuses, methods, and systems for neural networksINTEL CORP·Filed 2021·Application pending·0 cites
- 0866US10339060B2Optimized caching agent with integrated directory cacheINTEL CORP·Filed 2016·Granted Jul 2, 2019·1 cites·25 claims
- 0963US9727475B2Method and apparatus for distributed snoop filteringINTEL CORP·Filed 2014·Granted Aug 8, 2017·1 cites·22 claims
- 1062US9507596B2Instruction and logic for prefetcher throttling based on counts of memory accesses to data sourcesINTEL CORP·Filed 2014·Granted Nov 29, 2016·1 cites·20 claims
- 1152US12204834B2Debugging architecture for system in package composed of multiple semiconductor chipsINTEL CORP·Filed 2020·Granted Jan 21, 2025·0 cites·20 claims
- 1236US9229879B2Power reduction using unmodified information in evicted cache linesKUMASHIKAR MAHESH K·Filed 2011·Granted Jan 5, 2016·0 cites·21 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →