Inventor · disambiguated record
Asit K. Mishra
Also filed as: MISHRA ASIT · MISHRA ASIT K
23 granted patents·5 pending applications·124 citations·filing 2013–2024
95Inventor score
Top patents by PatentIndex Score
28 records- 0198US10275243B2Interruptible and restartable matrix multiplication instructions, processors, methods, and systemsINTEL CORP·Filed 2016·Granted Apr 30, 2019·23 cites·20 claims
- 0297US11093277B2Systems, methods, and apparatuses for heterogeneous computingINTEL CORP·Filed 2020·Granted Aug 17, 2021·6 cites·25 claims
- 0396US11698787B2Interruptible and restartable matrix multiplication instructions, processors, methods, and systemsINTEL CORP·Filed 2021·Granted Jul 11, 2023·3 cites·17 claims
- 0496US11693691B2Systems, methods, and apparatuses for heterogeneous computingINTEL CORP·Filed 2021·Granted Jul 4, 2023·4 cites·11 claims
- 0593US11373088B2Machine learning accelerator mechanismINTEL CORP·Filed 2017·Granted Jun 28, 2022·28 cites·25 claims
- 0693US11113053B2Data element comparison processors, methods, systems, and instructionsINTEL CORP·Filed 2019·Granted Sep 7, 2021·8 cites·20 claims
- 0793US10776110B2Apparatus and method for adaptable and efficient lane-wise tensor processingINTEL CORP·Filed 2018·Granted Sep 15, 2020·20 cites·27 claims
- 0893US10489063B2Memory-to-memory instructions to accelerate sparse-matrix by dense-vector and sparse-vector by dense-vector multiplicationINTEL CORP·Filed 2016·Granted Nov 26, 2019·10 cites·20 claims
- 0991US11416281B2Systems, methods, and apparatuses for heterogeneous computingINTEL CORP·Filed 2016·Granted Aug 16, 2022·4 cites·28 claims
- 1090US12135981B2Systems, methods, and apparatuses for heterogeneous computingINTEL CORP·Filed 2023·Granted Nov 5, 2024·1 cites·20 claims
- 1189US10275247B2Apparatuses and methods to accelerate vector multiplication of vector elements having matching indicesINTEL CORP·Filed 2015·Granted Apr 30, 2019·7 cites·24 claims
- 1288US9996361B2Byte and nibble sort instructions that produce sorted destination register and destination index mappingINTEL CORP·Filed 2015·Granted Jun 12, 2018·5 cites·20 claims
- 1387US2025138823A1Interruptible and restartable matrix multiplication instructions, processors, methods, and systemsINTEL CORP·Filed 2024·Application pending·0 cites
- 1485US12039435B2Machine learning accelerator mechanismINTEL CORP·Filed 2022·Granted Jul 16, 2024·1 cites·24 claims
- 1582US12204898B2Interruptible and restartable matrix multiplication instructions, processors, methods, and systemsINTEL CORP·Filed 2023·Granted Jan 21, 2025·0 cites·24 claims
- 1682US2025123881A1Systems, methods, and apparatuses for heterogeneous computingINTEL CORP·Filed 2024·Application pending·0 cites
- 1781US12050912B2Interruptible and restartable matrix multiplication instructions, processors, methods, and systemsINTEL CORP·Filed 2023·Granted Jul 30, 2024·0 cites·20 claims
- 1878US12417380B2Machine learning accelerator mechanismINTEL CORP·Filed 2024·Granted Sep 16, 2025·0 cites·20 claims
- 1974US10409613B2Processing devices to perform a key value lookup instructionINTEL CORP·Filed 2015·Granted Sep 10, 2019·2 cites·19 claims
- 2067US11048508B2Interruptible and restartable matrix multiplication instructions, processors, methods, and systemsINTEL CORP·Filed 2019·Granted Jun 29, 2021·0 cites·23 claims
- 2163US10198264B2Sorting data and merging sorted data in an instruction set architectureINTEL CORP·Filed 2015·Granted Feb 5, 2019·1 cites·25 claims
- 2262US9405724B2Reconfigurable apparatus for hierarchical collective networks with bypass modeINTEL CORP·Filed 2013·Granted Aug 2, 2016·1 cites·21 claims
- 2359US11379229B2Apparatus and method for adaptable and efficient lane-wise tensor processingINTEL CORP·Filed 2020·Granted Jul 5, 2022·0 cites·18 claims
- 2459US10635448B2Byte and nibble sort instructions that produce sorted destination register and destination index mappingINTEL CORP·Filed 2018·Granted Apr 28, 2020·0 cites·20 claims
- 2552US10423411B2Data element comparison processors, methods, systems, and instructionsINTEL CORP·Filed 2015·Granted Sep 24, 2019·0 cites·23 claims
- 2646US2015178092A1Hierarchical and parallel partition networksMISHRA ASIT K·Filed 2013·Application pending·0 cites
- 2744US2020050452A1Systems, apparatuses, and methods for generating an index by sort order and reordering elements based on sort orderINTEL CORP·Filed 2019·Application pending·0 cites
- 2838US2017185413A1Processing devices to perform a conjugate permute instructionINTEL CORP·Filed 2015·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →