Inventor · disambiguated record
Ashok Pachamuthu
Also filed as: PACHAMUTHU ASHOK
7 granted patents·2 pending applications·25 citations·filing 2017–2021
81Inventor score
Files withMICRON TECHNOLOGY INC9
Top patents by PatentIndex Score
9 records- 0194US11037910B2Semiconductor device having laterally offset stacked semiconductor diesMICRON TECHNOLOGY INC·Filed 2020·Granted Jun 15, 2021·4 cites·19 claims
- 0293US10103038B1Thrumold post package with reverse build up hybrid additive structureMICRON TECHNOLOGY INC·Filed 2017·Granted Oct 16, 2018·11 cites·25 claims
- 0385US10325874B2Device module having a plurality of dies electrically connected by postsMICRON TECHNOLOGY INC·Filed 2018·Granted Jun 18, 2019·4 cites·20 claims
- 0484US10192843B1Methods of making semiconductor device modules with increased yieldMICRON TECHNOLOGY INC·Filed 2017·Granted Jan 29, 2019·4 cites·20 claims
- 0579US10586780B2Semiconductor device modules including a die electrically connected to posts and related methodsMICRON TECHNOLOGY INC·Filed 2019·Granted Mar 10, 2020·2 cites·19 claims
- 0666US11929349B2Semiconductor device having laterally offset stacked semiconductor diesMICRON TECHNOLOGY INC·Filed 2021·Granted Mar 12, 2024·0 cites·21 claims
- 0757US10593568B2Thrumold post package with reverse build up hybrid additive structureMICRON TECHNOLOGY INC·Filed 2018·Granted Mar 17, 2020·0 cites·20 claims
- 0850US2019067248A1Semiconductor device having laterally offset stacked semiconductor diesMICRON TECHNOLOGY INC·Filed 2017·Application pending·0 cites
- 0936US2019067034A1Hybrid additive structure stackable memory die using wire bondMICRON TECHNOLOGY INC·Filed 2017·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →