Inventor · disambiguated record
Asaf Rubinstein
Also filed as: RUBINSTEIN ASAF
15 granted patents·5 pending applications·18 citations·filing 2011–2024
87Inventor score
Top patents by PatentIndex Score
20 records- 0187US9559726B2Use of error correcting code to carry additional data bitsINTEL CORP·Filed 2015·Granted Jan 31, 2017·7 cites·24 claims
- 0283US10296333B2SIMD variable shift and rotate using control manipulationINTEL CORP·Filed 2016·Granted May 21, 2019·5 cites·23 claims
- 0381US10055360B2Apparatus and method for shared least recently used (LRU) policy between multiple cache levelsINTEL CORP·Filed 2015·Granted Aug 21, 2018·3 cites·25 claims
- 0475US9710054B2Programmable power management agentINTEL CORP·Filed 2015·Granted Jul 18, 2017·2 cites·14 claims
- 0558US10657070B2Apparatus and method for shared least recently used (LRU) policy between multiple cache levelsINTEL CORP·Filed 2018·Granted May 19, 2020·0 cites·20 claims
- 0657US2025321799A1Apparatus and method for dynamic reassignment of system resources among active cores and ip blocksDIAMAND ISRAEL·Filed 2024·Application pending·0 cites
- 0756US10324718B2Packed rotate processors, methods, systems, and instructionsINTEL CORP·Filed 2018·Granted Jun 18, 2019·0 cites·19 claims
- 0856US2025307150A1Apparatus and method for home agent supporting caching agents with different coherency protocolsINTEL CORP·Filed 2024·Application pending·0 cites
- 0955US10761594B2Programmable power management agentINTEL CORP·Filed 2017·Granted Sep 1, 2020·0 cites·19 claims
- 1054US10635593B2Create page locality in cache controller cache allocationINTEL CORP·Filed 2017·Granted Apr 28, 2020·0 cites·18 claims
- 1153US9529591B2SIMD variable shift and rotate using control manipulationRUBINSTEIN ASAF·Filed 2011·Granted Dec 27, 2016·1 cites·29 claims
- 1251US11042315B2Dynamically programmable memory test traffic routerINTEL CORP·Filed 2018·Granted Jun 22, 2021·0 cites·22 claims
- 1350US9846648B2Create page locality in cache controller cache allocationINTEL CORP·Filed 2015·Granted Dec 19, 2017·0 cites·22 claims
- 1450US2024220408A1Dynamic allocation schemes in memory side cache for bandwidth and performance optimizationINTEL CORP·Filed 2022·Application pending·0 cites
- 1547US10915453B2Multi level system memory having different caching structures and memory controller that supports concurrent look-up into the different caching structuresINTEL CORP·Filed 2016·Granted Feb 9, 2021·0 cites·18 claims
- 1646US2024220410A1Leveraging System Cache for Performance CoresINTEL CORP·Filed 2022·Application pending·0 cites
- 1745US10304418B2Operating system transparent system memory abandonmentINTEL CORP·Filed 2016·Granted May 28, 2019·0 cites·12 claims
- 1845US10153784B2Use of error correcting code to carry additional data bitsINTEL CORP·Filed 2017·Granted Dec 11, 2018·0 cites·21 claims
- 1940US2020226066A1Apparatus and method for efficient management of multi-level memoryINTEL CORP·Filed 2020·Application pending·0 cites
- 2039US10678706B2Cache memory with scrubber logicINTEL CORP·Filed 2018·Granted Jun 9, 2020·0 cites·18 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →