Inventor · disambiguated record
Baris Ozgul
Also filed as: OZGUL BARIS
28 granted patents·3 pending applications·203 citations·filing 2009–2024
96Inventor score
Top patents by PatentIndex Score
31 records- 0196US11336287B1Data processing engine array architecture with memory tilesXILINX INC·Filed 2021·Granted May 17, 2022·26 cites·20 claims
- 0296US10866753B2Data processing engine arrangement in a deviceXILINX INC·Filed 2018·Granted Dec 15, 2020·15 cites·10 claims
- 0396US10747690B2Device with data processing engine arrayXILINX INC·Filed 2018·Granted Aug 18, 2020·19 cites·20 claims
- 0495US11669464B1Multi-addressing mode for DMA and non-sequential read and write patternsXILINX INC·Filed 2020·Granted Jun 6, 2023·9 cites·20 claims
- 0595US11520717B1Memory tiles in data processing engine arrayXILINX INC·Filed 2021·Granted Dec 6, 2022·11 cites·20 claims
- 0694US11323391B1Multi-port stream switch for stream interconnect networkXILINX INC·Filed 2020·Granted May 3, 2022·6 cites·20 claims
- 0794US10824584B1Device with data processing engine array that enables partial reconfigurationXILINX INC·Filed 2018·Granted Nov 3, 2020·13 cites·20 claims
- 0891US10635622B2System-on-chip interface architectureXILINX INC·Filed 2018·Granted Apr 28, 2020·10 cites·8 claims
- 0990US9189458B1Parameter estimationXILINX INC·Filed 2013·Granted Nov 17, 2015·16 cites·20 claims
- 1089US8301139B2Femtocell configuration using spectrum sensingLOTZE JORG·Filed 2009·Granted Oct 30, 2012·53 cites·20 claims
- 1185US10990552B1Streaming interconnect architecture for data processing engine arrayXILINX INC·Filed 2018·Granted Apr 27, 2021·4 cites·20 claims
- 1284US11113223B1Dual mode interconnectXILINX INC·Filed 2018·Granted Sep 7, 2021·4 cites·23 claims
- 1383US11573726B1Data processing engine arrangement in a deviceXILINX INC·Filed 2020·Granted Feb 7, 2023·1 cites·8 claims
- 1482US11016822B1Cascade streaming between data processing engines in an arrayXILINX INC·Filed 2018·Granted May 25, 2021·3 cites·21 claims
- 1582US10747531B1Core for a data processing engine in an integrated circuitXILINX INC·Filed 2018·Granted Aug 18, 2020·3 cites·20 claims
- 1679US11379389B1Communicating between data processing engines using shared memoryXILINX INC·Filed 2018·Granted Jul 5, 2022·2 cites·20 claims
- 1779US2024256482A1Device with data processing engine array that enables partial reconfigurationXILINX INC·Filed 2024·Application pending·0 cites
- 1878US11567881B1Event-based debug, trace, and profile in device with data processing engine arrayXILINX INC·Filed 2018·Granted Jan 31, 2023·2 cites·20 claims
- 1977US12105667B2Device with data processing engine array that enables partial reconfigurationXILINX INC·Filed 2023·Granted Oct 1, 2024·0 cites·20 claims
- 2077US11972132B2Data processing engine arrangement in a deviceXILINX INC·Filed 2022·Granted Apr 30, 2024·0 cites·19 claims
- 2177US10579559B1Stall logic for a data processing engine in an integrated circuitXILINX INC·Filed 2018·Granted Mar 3, 2020·2 cites·19 claims
- 2276US11443091B1Data processing engines with cascade connected coresXILINX INC·Filed 2020·Granted Sep 13, 2022·1 cites·20 claims
- 2375US11061673B1Data selection network for a data processing engine in an integrated circuitXILINX INC·Filed 2018·Granted Jul 13, 2021·2 cites·16 claims
- 2471US11372803B2Data processing engine tile architecture for an integrated circuitXILINX INC·Filed 2018·Granted Jun 28, 2022·1 cites·19 claims
- 2568US11853235B2Communicating between data processing engines using shared memoryXILINX INC·Filed 2022·Granted Dec 26, 2023·0 cites·20 claims
- 2668US11599498B1Device with data processing engine array that enables partial reconfigurationXILINX INC·Filed 2020·Granted Mar 7, 2023·0 cites·20 claims
- 2766US11730325B2Dual mode interconnectXILINX INC·Filed 2021·Granted Aug 22, 2023·0 cites·18 claims
- 2855US12067406B2Multiple overlays for use with a data processing arrayXILINX INC·Filed 2022·Granted Aug 20, 2024·0 cites·20 claims
- 2955US10623222B2Vectorized peak detection for signal processingXILINX INC·Filed 2018·Granted Apr 14, 2020·0 cites·18 claims
- 3048US2025370750A1Unaligned load and store in a coreXILINX INC·Filed 2024·Application pending·0 cites
- 3139US2023058749A1Adaptive matrix multipliersXILINX INC·Filed 2022·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →