Inventor · disambiguated record
Balaji Upputuri
Also filed as: UPPUTURI BALAJI
8 granted patents·2 citations·filing 2012–2023
73Inventor score
Top patents by PatentIndex Score
8 records- 0187US12025661B1Power-sensitive scan-chain testingMARVELL ASIA PTE LTD·Filed 2023·Granted Jul 2, 2024·1 cites·24 claims
- 0263US12241931B1Method and apparatus for capture clock control to minimize toggling during testingMARVELL ASIA PTE LTD·Filed 2023·Granted Mar 4, 2025·0 cites·20 claims
- 0357US9086458B2Q-gating cell architecture to satiate the launch-off-shift (LOS) testing and an algorithm to identify best Q-gating candidatesIBM·Filed 2013·Granted Jul 21, 2015·1 cites·20 claims
- 0455US11662382B1Method and apparatus for contemporary test time reduction for JTAGMARVELL ASIA PTE LTD·Filed 2021·Granted May 30, 2023·0 cites·20 claims
- 0554US11768239B1Method and apparatus for timing-annotated scan-chain testing using parallel testbenchMARVELL ASIA PTE LTD·Filed 2022·Granted Sep 26, 2023·0 cites·20 claims
- 0643US8898604B1Algorithm to identify best Q-gating candidates and a Q-gating cell architecture to satiate the launch-off-shift (LOS) testingIBM·Filed 2013·Granted Nov 25, 2014·0 cites·20 claims
- 0741US8776006B1Delay defect testing of power drop effects in integrated circuitsIBM·Filed 2013·Granted Jul 8, 2014·0 cites·20 claims
- 0831US8990648B2Optimized synchronous scan flip flop circuitLAKSHMIPATHY RAVI·Filed 2012·Granted Mar 24, 2015·0 cites·12 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →