Inventor · disambiguated record
Bau-Ming Wang
Also filed as: WANG BAU-MING
7 granted patents·11 pending applications·3 citations·filing 2011–2025
73Inventor score
Top patents by PatentIndex Score
18 records- 0194US11374108B2Fin semiconductor device having a stepped gate spacer sidewallTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Jun 28, 2022·3 cites·20 claims
- 0279US2025357125A1Hot Ion Implantation for Condensation Defect ReductionTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 0379US2025120146A1Semiconductor device having a doped fin wellTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Application pending·0 cites
- 0479US2025344493A1Doped well for semiconductor devicesTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 0576US12211901B2Semiconductor device having a doped fin wellTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Jan 28, 2025·0 cites·20 claims
- 0675US12087841B2Method of manufacturing gate spacers with stepped sidewalls by removing vertical portions of a helmet layerTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Sep 10, 2024·0 cites·20 claims
- 0775US2025336677A1Etch Stop Region for Semiconductor Device Substrate ThinningTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 0871US2025022712A1Hot ion implantation for condensation defect reductionTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Application pending·0 cites
- 0968US11450743B2Method of forming a semiconductor device with implantation of impurities at high temperatureTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Sep 20, 2022·0 cites·20 claims
- 1068US2025218856A1Method and Device to Reduce Epitaxial Defects Due to Contact Stress Upon a Semiconductor WaferTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 1165US2024079239A1Etch Stop Region for Semiconductor Device Substrate ThinningTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Application pending·0 cites
- 1265US2022406774A1Doped well for semiconductor devicesTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Application pending·0 cites
- 1362US2025385125A1Sti protection layer formation through implantation and the structures thereofTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Application pending·0 cites
- 1459US12283515B2Method and device to reduce epitaxial defects due to contact stress upon a semicondcutor waferTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Apr 22, 2025·0 cites·20 claims
- 1559US10741667B2Method of manufacturing a protective stack on a semiconductor finTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2018·Granted Aug 11, 2020·0 cites·20 claims
- 1659US2025285988A1Doped well and alignment mark for semiconductor devicesTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Application pending·0 cites
- 1757US2025374611A1Protective hard mask and methods of making sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Application pending·0 cites
- 1828US8906778B2Method of semiconductor manufacturing processWU YEWCHUNG SERMON·Filed 2011·Granted Dec 9, 2014·0 cites·16 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →