Inventor · disambiguated record
Benedikt Geukes
Also filed as: GEUKES BENEDIKT
18 granted patents·2 pending applications·19 citations·filing 2011–2021
90Inventor score
Top patents by PatentIndex Score
20 records- 0193US11663381B2Clock mapping in an integrated circuit designIBM·Filed 2021·Granted May 30, 2023·4 cites·24 claims
- 0278US10026498B1Simultaneous scan chain initialization with disparate latchesIBM·Filed 2017·Granted Jul 17, 2018·3 cites·17 claims
- 0375US10199121B2Simultaneous scan chain initialization with disparate latchesIBM·Filed 2018·Granted Feb 5, 2019·2 cites·2 claims
- 0474US9202060B2Method for secure self-booting of an electronic deviceIBM·Filed 2012·Granted Dec 1, 2015·4 cites·17 claims
- 0573US10096377B1Simultaneous scan chain initialization with disparate latchesIBM·Filed 2017·Granted Oct 9, 2018·2 cites·1 claims
- 0671US8972808B2Controlling scan access to a scan chainIBM·Filed 2013·Granted Mar 3, 2015·2 cites·12 claims
- 0769US9727754B2Protecting chip settings using secured scan chainsIBM·Filed 2015·Granted Aug 8, 2017·1 cites·20 claims
- 0857US10156610B2On-chip sequence profilerIBM·Filed 2017·Granted Dec 18, 2018·0 cites·19 claims
- 0957US9222973B2Protecting chip settings using secured scan chainsGEUKES BENEDIKT·Filed 2012·Granted Dec 29, 2015·1 cites·18 claims
- 1057US2018321315A1On-chip sequence profilerIBM·Filed 2017·Application pending·0 cites
- 1154US10658062B2Simultaneous scan chain initialization with disparate latchesIBM·Filed 2019·Granted May 19, 2020·0 cites·8 claims
- 1253US10586606B2Simultaneous scan chain initialization with disparate latchesIBM·Filed 2019·Granted Mar 10, 2020·0 cites·17 claims
- 1352US8984355B2Efficiency of compression of data pagesIBM·Filed 2012·Granted Mar 17, 2015·0 cites·8 claims
- 1451US10838449B2Automatic detection of clock grid misalignments and automatic realignmentIBM·Filed 2018·Granted Nov 17, 2020·0 cites·20 claims
- 1551US9110137B2Method for JTAG-driven remote scanningIBM·Filed 2013·Granted Aug 18, 2015·0 cites·8 claims
- 1645US12204832B2Logical clock connection in an integrated circuit designIBM·Filed 2021·Granted Jan 21, 2025·0 cites·22 claims
- 1744US2023074528A1Iterative design of an integrated circuit designIBM·Filed 2021·Application pending·0 cites
- 1842US8914693B2Apparatus for JTAG-driven remote scanningDOERR MARTIN·Filed 2012·Granted Dec 16, 2014·0 cites·12 claims
- 1941US11907634B2Automating addition of power supply rails, fences, and level translators to a modular circuit designIBM·Filed 2021·Granted Feb 20, 2024·0 cites·25 claims
- 2039US8656235B2Verifying and detecting boundary scan cells to input/output mappingGEUKES BENEDIKT·Filed 2011·Granted Feb 18, 2014·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →