Inventor · disambiguated record
Bee Yee Ng
Also filed as: NG BEE YEE
16 granted patents·6 pending applications·72 citations·filing 2002–2024
90Inventor score
Top patents by PatentIndex Score
22 records- 0185US6988258B2Mask-programmable logic device with building block architectureALTERA CORP·Filed 2002·Granted Jan 17, 2006·33 cites·39 claims
- 0283US7265587B1LVDS output buffer pre-emphasis methods and apparatusALTERA CORP·Filed 2005·Granted Sep 4, 2007·12 cites·19 claims
- 0382US9705504B1Power gated lookup table circuitryALTERA CORP·Filed 2016·Granted Jul 11, 2017·5 cites·18 claims
- 0480US9047934B1Timing signal adjustment for data storageALTERA CORP·Filed 2013·Granted Jun 2, 2015·9 cites·20 claims
- 0567US12411174B2Circuits and methods for configurable scan chainsINTEL CORP·Filed 2022·Granted Sep 9, 2025·0 cites·20 claims
- 0665US10191661B1Lutram dummy read scheme during error detection and correctionALTERA CORP·Filed 2016·Granted Jan 29, 2019·1 cites·13 claims
- 0759US2024137026A1Techniques For Storing States Of Signals In Configurable Storage CircuitsALTERA CORP·Filed 2023·Application pending·0 cites
- 0858US12197360B2At-speed burst sampling for user registersINTEL CORP·Filed 2021·Granted Jan 14, 2025·0 cites·20 claims
- 0958US7639047B1Techniques for reducing clock skew in clock routing networksALTERA CORP·Filed 2008·Granted Dec 29, 2009·2 cites·20 claims
- 1058US7565390B1Circuitry for facilitating performance of multiply-accumulate operations in programmable logic devicesALTERA CORP·Filed 2005·Granted Jul 21, 2009·3 cites·26 claims
- 1158US7305640B1Programmable soft macro memory using gate array base cellsALTERA CORP·Filed 2004·Granted Dec 4, 2007·6 cites·31 claims
- 1257US2025061257A1Techniques For Reconfiguring Lookup Tables Using Memory During User ModeALTERA CORP·Filed 2024·Application pending·0 cites
- 1354US12086460B2Non-destructive readback and writeback for integrated circuit deviceINTEL CORP·Filed 2020·Granted Sep 10, 2024·0 cites·18 claims
- 1451US2024354480A1Programmable Logic Circuits Using Lookup Tables (LUTs) Augmented with Configurable Logic GatesCHROMCZAK JEFFREY·Filed 2024·Application pending·0 cites
- 1549US2022244867A1Fabric Memory Network-On-Chip Extension to ALM Registers and LUTRAMNG BEE YEE·Filed 2022·Application pending·0 cites
- 1648US10686446B2Power gated lookup table circuitryALTERA CORP·Filed 2017·Granted Jun 16, 2020·0 cites·20 claims
- 1748US2024348252A1Enhanced Adaptive Logic Circuitry with Improved Function Coverage and Packing AbilityCHROMCZAK JEFFREY·Filed 2024·Application pending·0 cites
- 1847US11749368B2Quick configurable universal register for a configurable integrated circuit dieINTEL CORP·Filed 2019·Granted Sep 5, 2023·0 cites·20 claims
- 1946US2025192785A1Techniques For Configurable Selection Between Hard Logic And Configurable Logic GatesALTERA CORP·Filed 2023·Application pending·0 cites
- 2039US7218141B2Techniques for implementing hardwired decoders in differential input circuitsALTERA CORP·Filed 2004·Granted May 15, 2007·1 cites·21 claims
- 2137US9972368B2Circuitry for reducing leakage current in configuration memoryALTERA CORP·Filed 2016·Granted May 15, 2018·0 cites·14 claims
- 2233US8037444B1Programmable control of mask-programmable integrated circuit devicesALTERA CORP·Filed 2006·Granted Oct 11, 2011·0 cites·18 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →