Inventor · disambiguated record
Benjamin J. Patella
Also filed as: PATELLA BENJAMIN J · PATELLA BENJAMIN JAMES
8 granted patents·2 pending applications·139 citations·filing 2002–2005
87Inventor score
Top patents by PatentIndex Score
10 records- 0189US7401245B2Count calibration for synchronous data transfer between clock domainsHEWLETT PACKARD DEVELOPMENT CO·Filed 2005·Granted Jul 15, 2008·24 cites·17 claims
- 0287US7595686B2Digital controller for high-frequency switching power suppliesUNIV COLORADO·Filed 2002·Granted Sep 29, 2009·41 cites·27 claims
- 0386US6927605B2System and method for dynamically varying a clock signalHEWLETT PACKARD DEVELOPMENT CO·Filed 2003·Granted Aug 9, 2005·40 cites·6 claims
- 0477US7394301B2System and method for dynamically varying a clock signalHEWLETT PACKARD DEVELOPMENT CO·Filed 2005·Granted Jul 1, 2008·7 cites·29 claims
- 0573US7100097B2Detection of bit errors in maskable content addressable memoriesINTEL CORP·Filed 2002·Granted Aug 29, 2006·19 cites·20 claims
- 0669US7477712B2Adaptable data path for synchronous data transfer between clock domainsHEWLETT PACKARD DEVELOPMENT CO·Filed 2005·Granted Jan 13, 2009·4 cites·19 claims
- 0757US7558317B2Edge calibration for synchronous data transfer between clock domainsHEWLETT PACKARD DEVELOPMENT CO·Filed 2005·Granted Jul 7, 2009·1 cites·28 claims
- 0844US6946877B2Circuit and associated methodologyHEWLETT PACKARD DEVELOPMENT CO·Filed 2003·Granted Sep 20, 2005·3 cites·19 claims
- 0934US2005007154A1System and method for evaluating the speed of a circuitFiled 2003·Application pending·0 cites
- 1030US2004015753A1Detection of bit errors in content addressable memoriesFiled 2002·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →