Inventor · disambiguated record
Bernard Previtali
Also filed as: PREVITALI BERNARD
16 granted patents·2 pending applications·16 citations·filing 2003–2021
87Inventor score
Files withCOMMISSARIAT ENERGIE ATOMIQUE12NEMOUCHI FABRICE2PREVITALI BERNARD2COMMISSARIAT L ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES1ST MICROELECTRONICS SA1
Top patents by PatentIndex Score
18 records- 0184US11152360B2Architecture of N and P transistors superposed with canal structure formed of nanowiresCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2019·Granted Oct 19, 2021·3 cites·6 claims
- 0273US9761583B2Manufacturing of self aligned interconnection elements for 3D integrated circuitsCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2016·Granted Sep 12, 2017·2 cites·14 claims
- 0372US8664104B2Method of producing a device with transistors strained by means of an external layerNEMOUCHI FABRICE·Filed 2012·Granted Mar 4, 2014·4 cites·14 claims
- 0463US8021986B2Method for producing a transistor with metallic source and drainCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2010·Granted Sep 20, 2011·2 cites·14 claims
- 0561US12237330B2Architecture with stacked N and P transistors with a channel structure formed of nanowiresCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2021·Granted Feb 25, 2025·0 cites·12 claims
- 0659US7491644B2Manufacturing process for a transistor made of thin layersCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2005·Granted Feb 17, 2009·2 cites·23 claims
- 0756US7709332B2Process for fabricating a field-effect transistor with self-aligned gatesCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2007·Granted May 4, 2010·2 cites·13 claims
- 0854US9093552B2Manufacturing method for a device with transistors strained by silicidation of source and drain zonesNEMOUCHI FABRICE·Filed 2012·Granted Jul 28, 2015·1 cites·12 claims
- 0944US8021934B2Method for making a transistor with metallic source and drainCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2009·Granted Sep 20, 2011·0 cites·7 claims
- 1043US7473588B2Method for insulating patterns formed in a thin film of oxidizable semi-conducting materialCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2005·Granted Jan 6, 2009·0 cites·17 claims
- 1142US7977195B2Method for manufacturing a field effect transistor with auto-aligned gridsCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2008·Granted Jul 12, 2011·0 cites·8 claims
- 1239US2014273480A1Method for producing a substrate provided with edge protectionST MICROELECTRONICS SA·Filed 2014·Application pending·0 cites
- 1338US10128332B2Method for fabricating an improved field effect deviceCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2016·Granted Nov 13, 2018·0 cites·17 claims
- 1437US9721850B2Method for making a three dimensional integrated electronic circuitCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2016·Granted Aug 1, 2017·0 cites·13 claims
- 1535US9461142B2Fabrication method of an improved field effect deviceCOMMISSARIAT Á L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES·Filed 2015·Granted Oct 4, 2016·0 cites·10 claims
- 1635US8796118B2Method of producing a three-dimensional integrated circuitPREVITALI BERNARD·Filed 2012·Granted Aug 5, 2014·0 cites·15 claims
- 1732US7425509B2Method for forming patterns aligned on either side of a thin filmCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2003·Granted Sep 16, 2008·0 cites·16 claims
- 1831US2007117324A1Vertical MOS transistor and fabrication processPREVITALI BERNARD·Filed 2006·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →