Inventor · disambiguated record
Bhavesh G. Bhakta
Also filed as: BHAKTA BHAVESH · BHAKTA BHAVESH G
17 granted patents·8 pending applications·94 citations·filing 1999–2025
92Inventor score
Top patents by PatentIndex Score
25 records- 0182US8653856B2Electronic device and method for bufferingPIEPENSTOCK OLIVER·Filed 2011·Granted Feb 18, 2014·9 cites·16 claims
- 0282US6636120B2Decimated digital phase-locked loop for high-speed implementationTEXAS INSTRUMENTS INC·Filed 2001·Granted Oct 21, 2003·16 cites·4 claims
- 0376US2025226830A1Methods and apparatus to retime data using a programmable delayTEXAS INSTRUMENTS INC·Filed 2025·Application pending·0 cites
- 0474US12289114B2Methods and apparatus to retime data using a programmable delayTEXAS INSTRUMENTS INC·Filed 2024·Granted Apr 29, 2025·0 cites·20 claims
- 0573US7443913B2High speed decision feedback equalizerTEXAS INSTRUMENTS INC·Filed 2004·Granted Oct 28, 2008·18 cites·23 claims
- 0672US7782932B2Circuit and method for evaluating the performance of an adaptive decision feedback equalizer-based serializer deserializer and serdes incorporating the sameTEXAS INSTRUMENTS INC·Filed 2004·Granted Aug 24, 2010·16 cites·14 claims
- 0771US7944252B1High performance LVDS driver for scalable supplyTEXAS INSTRUMENTS INC·Filed 2009·Granted May 17, 2011·7 cites·21 claims
- 0868US12028079B2Methods and apparatus to retime data using a programmable delayTEXAS INSTRUMENTS INC·Filed 2023·Granted Jul 2, 2024·0 cites·20 claims
- 0967US9503104B2Low power loss of lock detectorTEXAS INSTRUMENTS INC·Filed 2015·Granted Nov 22, 2016·2 cites·20 claims
- 1064US6813111B2Implementation method of digital phase-locked loopTEXAS INSTRUMENTS INC·Filed 2001·Granted Nov 2, 2004·5 cites·2 claims
- 1163US7733261B2Hybrid analog to digital converter circuit and methodTEXAS INSTRUMENTS INC·Filed 2008·Granted Jun 8, 2010·6 cites·21 claims
- 1255US12316334B2Method and circuit for DLL locking mechanism for wide range harmonic detection and false lock detectionTEXAS INSTRUMENTS INC·Filed 2023·Granted May 27, 2025·0 cites·20 claims
- 1355US12231527B2Clock recovery trainingTEXAS INSTRUMENTS INC·Filed 2021·Granted Feb 18, 2025·0 cites·14 claims
- 1455US2025141652A1Clock recovery trainingTEXAS INSTRUMENTS INC·Filed 2025·Application pending·0 cites
- 1548US7315182B2Circuit to observe internal clock and control signals in a receiver with integrated termination and common mode controlTEXAS INSTRUMENTS INC·Filed 2004·Granted Jan 1, 2008·7 cites·15 claims
- 1648US7277828B2Methodology for designing high speed receivers below a target bit-error-rateTEXAS INSTRUMENTS INC·Filed 2004·Granted Oct 2, 2007·0 cites·14 claims
- 1746US6256159B1Method and circuit for dibit detectionTEXAS INSTRUMENTS INC·Filed 1999·Granted Jul 3, 2001·7 cites·16 claims
- 1839US2002172305A1Fixed decision delay detectors for timing recovery loopFiled 2001·Application pending·0 cites
- 1937US7349932B2High performance FIR filterTEXAS INSTRUMENTS INC·Filed 2004·Granted Mar 25, 2008·0 cites·6 claims
- 2036US6738206B2Decision error compensation technique for decision-directed timing recovery loopTEXAS INSTRUMENTS INC·Filed 2001·Granted May 18, 2004·1 cites·1 claims
- 2134US2005193290A1Built-in self test method and apparatus for jitter transfer, jitter tolerance, and FIFO data bufferFiled 2004·Application pending·0 cites
- 2234US2005162193A1High performance sense amplifiersTEXAS INSTRUMENTS INC·Filed 2004·Application pending·0 cites
- 2333US2016048152A1Current mirror with depletion mode mos and embedded noise filterTEXAS INSTRUMENTS INC·Filed 2015·Application pending·0 cites
- 2433US2011193598A1Efficient retimer for clock dividersTEXAS INSTRUMENTS INC·Filed 2010·Application pending·0 cites
- 2529US2002141089A1Timing recovery loop latency reduction via loop filter pre-calculationFiled 2001·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →