Inventor · disambiguated record
Bijit Halder
Also filed as: HALDER BIJIT
7 granted patents·4 pending applications·53 citations·filing 2000–2011
83Inventor score
Top patents by PatentIndex Score
11 records- 0172US6788236B2Method and system for implementing a sigma delta analog-to-digital converterGLOBESPAN VIRATA INC·Filed 2002·Granted Sep 7, 2004·21 cites·20 claims
- 0268USRE43790EDelay line correlatorBABANEZHAD JOSEPH N·Filed 2011·Granted Nov 6, 2012·2 cites·26 claims
- 0363US7076514B2Method and system for computing pre-equalizer coefficientsCONEXANT INC·Filed 2002·Granted Jul 11, 2006·10 cites·18 claims
- 0459US6769090B1Unified technique for multi-rate trellis coding and decodingVIRATA CORP·Filed 2000·Granted Jul 27, 2004·12 cites·26 claims
- 0554US6934328B1Relaxed, more optimum training for modems and the likeVIRATA CORP·Filed 2000·Granted Aug 23, 2005·4 cites·12 claims
- 0647US8811599B2Systems, circuits and methods for dual transformer duplexingBABANEZHAD JOSEPH N·Filed 2010·Granted Aug 19, 2014·0 cites·15 claims
- 0747US6693975B2Low-order HDSL2 transmit filterVIRATA CORP·Filed 2001·Granted Feb 17, 2004·4 cites·16 claims
- 0838US2003112966A1Method and system for implementing a reduced complexity dual rate echo cancellerFiled 2001·Application pending·0 cites
- 0936US2003112861A1Method and system for adaptively training time domain equalizersFiled 2001·Application pending·0 cites
- 1035US2003118177A1Method and system for implementing a reduced complexity dual rate echo cancellerFiled 2001·Application pending·0 cites
- 1134US2003112887A1Method and system for implementing weighted vector error echo cancellersFiled 2001·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →