Inventor · disambiguated record
Bilal Khalaf
Also filed as: KHALAF BILAL
20 granted patents·3 pending applications·26 citations·filing 2015–2023
89Inventor score
Top patents by PatentIndex Score
23 records- 0194US9871007B2Packaged integrated circuit device with cantilever structureINTEL CORP·Filed 2015·Granted Jan 16, 2018·20 cites·9 claims
- 0281US11145632B2High density die package configuration on system boardsINTEL CORP·Filed 2017·Granted Oct 12, 2021·3 cites·20 claims
- 0374US10879152B2Through mold via (TMV) using stacked modular mold ringsINTEL CORP·Filed 2016·Granted Dec 29, 2020·2 cites·18 claims
- 0466US11710674B2Embedded component and methods of making the sameINTEL CORP·Filed 2022·Granted Jul 25, 2023·0 cites·12 claims
- 0565US11848311B2Microelectronic packages having a die stack and a device within the footprint of the die stackINTEL CORP·Filed 2022·Granted Dec 19, 2023·0 cites·18 claims
- 0664US10847450B2Compact wirebonding in stacked-chip system in package, and methods of making sameINTEL CORP·Filed 2016·Granted Nov 24, 2020·1 cites·9 claims
- 0760US11700696B2Buried electrical debug access portINTEL CORP·Filed 2021·Granted Jul 11, 2023·0 cites·13 claims
- 0855US2024321609A1Methods and systems for controlling underfill bleed-out in semiconductor packagingSK HYNIX NAND PRODUCT SOLUTIONS CORP DBA SOLIDIGM·Filed 2023·Application pending·0 cites
- 0952US2024179844A1Reducing printed circuit board area for single-sided printed circuit boardSK HYNIX NAND PRODUCT SOLUTIONS CORP DBA SOLIDIGM·Filed 2022·Application pending·0 cites
- 1050US10490516B2Packaged integrated circuit device with cantilever structureINTEL CORP·Filed 2018·Granted Nov 26, 2019·0 cites·5 claims
- 1150US10090261B2Microelectronic package debug access ports and methods of fabricating the sameINTEL CORP·Filed 2017·Granted Oct 2, 2018·0 cites·14 claims
- 1249US11329027B2Microelectronic packages having a die stack and a device within the footprint of the die stackINTEL CORP·Filed 2016·Granted May 10, 2022·0 cites·18 claims
- 1349US9646952B2Microelectronic package debug access portsINTEL CORP·Filed 2015·Granted May 9, 2017·0 cites·16 claims
- 1448US11064612B2Buried electrical debug access portINTEL CORP·Filed 2016·Granted Jul 13, 2021·0 cites·17 claims
- 1547US11315843B2Embedded component and methods of making the sameINTEL CORP·Filed 2016·Granted Apr 26, 2022·0 cites·16 claims
- 1646US11894334B2Dual head capillary design for vertical wire bondINTEL CORP·Filed 2018·Granted Feb 6, 2024·0 cites·10 claims
- 1746US11817438B2System in package with interconnected modulesINTEL CORP·Filed 2019·Granted Nov 14, 2023·0 cites·20 claims
- 1843US11811182B2Solderless BGA interconnectINTEL CORP·Filed 2018·Granted Nov 7, 2023·0 cites·21 claims
- 1943US11373974B2Electronic device packages and methods for maximizing electrical current to dies and minimizing bond finger sizeINTEL CORP·Filed 2016·Granted Jun 28, 2022·0 cites·18 claims
- 2042US9972610B2System-in-package logic and method to control an external packaged memory deviceINTEL CORP·Filed 2015·Granted May 15, 2018·0 cites·20 claims
- 2141US10304814B2I/O layout footprint for multiple 1LM/2LM configurationsINTEL CORP·Filed 2017·Granted May 28, 2019·0 cites·19 claims
- 2240US10475766B2Microelectronics package providing increased memory component densityINTEL CORP·Filed 2017·Granted Nov 12, 2019·0 cites·16 claims
- 2337US2019006331A1Electronics package devices with through-substrate-vias having pitches independent of substrate thicknessINTEL CORP·Filed 2017·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →