Inventor · disambiguated record
Bih-Tiao Lin
Also filed as: LIN BIH-TIAO
16 granted patents·2 pending applications·444 citations·filing 1997–2005
93Inventor score
Top patents by PatentIndex Score
18 records- 0195US6071789AMethod for simultaneously fabricating a DRAM capacitor and metal interconnectionsVANGUARD INT SEMICONDUCT CORP·Filed 1998·Granted Jun 6, 2000·265 cites·19 claims
- 0284US6343977B1Multi-zone conditioner for chemical mechanical polishing systemWORLDWIDE SEMICONDUCTOR MFG·Filed 2000·Granted Feb 5, 2002·27 cites·14 claims
- 0378US6524950B1Method of fabricating copper damasceneTAIWAN SEMICONDUCTOR MFG·Filed 2000·Granted Feb 25, 2003·28 cites·10 claims
- 0471US6821895B2Dynamically adjustable slurry feed arm for wafer edge profile improvement in CMPTAIWAN SEMICONDUCTOR MFG·Filed 2003·Granted Nov 23, 2004·15 cites·20 claims
- 0568US6604849B2Slurry dilution system with an ultrasonic vibrator capable of in-situ adjustment of slurry concentrationTAIWAN SEMICONDUCTOR MFG·Filed 2001·Granted Aug 12, 2003·21 cites·15 claims
- 0665US5888124AApparatus for polishing and cleaning a waferVANGUARD INT SEMICONDUCT CORP·Filed 1997·Granted Mar 30, 1999·30 cites·19 claims
- 0755US6140240AMethod for eliminating CMP induced microscratchesVANGUARD INT SEMICONDUCT CORP·Filed 1999·Granted Oct 31, 2000·19 cites·17 claims
- 0853US7685667B2Post-CMP cleaning systemTAIWAN SEMICONDUCTOR MFG·Filed 2005·Granted Mar 30, 2010·1 cites·12 claims
- 0945US6660629B2Chemical mechanical polishing method for fabricating copper damascene structureTAIWAN SEMICONDUCTOR MFG·Filed 2002·Granted Dec 9, 2003·2 cites·9 claims
- 1045US6180489B1Formation of finely controlled shallow trench isolation for ULSI processVANGUARD INT SEMICONDUCT CORP·Filed 1999·Granted Jan 30, 2001·12 cites·20 claims
- 1144US6054017AChemical mechanical polishing pad with controlled polish rateVANGUARD INT SEMICONDUCT CORP·Filed 1998·Granted Apr 25, 2000·10 cites·20 claims
- 1243US6454917B1High throughput and high performance copper electroplating toolTAIWAN SEMICONDUCTOR MFG·Filed 2000·Granted Sep 24, 2002·0 cites·17 claims
- 1341US6277751B1Method of planarizationWORLDWIDE SEMICONDUCTOR MFG·Filed 1999·Granted Aug 21, 2001·9 cites·9 claims
- 1436US2004235297A1Reverse electroplating for damascene conductive region formationFiled 2003·Application pending·0 cites
- 1535US6037259AMethod for forming identifying characters on a silicon waferVANGUARD INT SEMICONDUCT CORP·Filed 1998·Granted Mar 14, 2000·5 cites·11 claims
- 1635US2002137305A1Fabrication method of shallow trench isolationFiled 2001·Application pending·0 cites
- 1729US6218307B1Method of fabricating shallow trench isolation structureTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Apr 17, 2001·0 cites·13 claims
- 1819US6089969APowder-proof apparatus for a PECVD reactor chamberVANGUARD INT SEMICONDUCT CORP·Filed 1998·Granted Jul 18, 2000·0 cites·2 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →