Inventor · disambiguated record
Boon Jin Ang
Also filed as: ANG BOON JIN
36 granted patents·456 citations·filing 2001–2017
97Inventor score
Top patents by PatentIndex Score
36 records- 0199US6525678B1Configuring a programmable logic deviceALTERA CORP·Filed 2001·Granted Feb 25, 2003·165 cites·19 claims
- 0293US8612814B1Memory error detection circuitryTAN JUN PIN·Filed 2010·Granted Dec 17, 2013·24 cites·14 claims
- 0388US8699291B1Memory circuitry with dynamic power controlCH NG CHIN GHEE·Filed 2012·Granted Apr 15, 2014·18 cites·19 claims
- 0487US7978493B1Data encoding scheme to reduce sense currentALTERA CORP·Filed 2008·Granted Jul 12, 2011·19 cites·10 claims
- 0585US7242218B2Techniques for combining volatile and non-volatile programmable logic on an integrated circuitALTERA CORP·Filed 2004·Granted Jul 10, 2007·28 cites·27 claims
- 0685US6988258B2Mask-programmable logic device with building block architectureALTERA CORP·Filed 2002·Granted Jan 17, 2006·33 cites·39 claims
- 0783US7265587B1LVDS output buffer pre-emphasis methods and apparatusALTERA CORP·Filed 2005·Granted Sep 4, 2007·12 cites·19 claims
- 0883US6489817B1Clock divider using positive and negative edge triggered state machinesALTERA CORP·Filed 2001·Granted Dec 3, 2002·28 cites·43 claims
- 0979US8533250B1Multiplier with built-in accumulatorFOO KOK YOONG·Filed 2009·Granted Sep 10, 2013·18 cites·20 claims
- 1079US8037377B1Techniques for performing built-in self-test of receiver channel having a serializerALTERA CORP·Filed 2008·Granted Oct 11, 2011·10 cites·22 claims
- 1178US8189362B2Data encoding scheme to reduce sense currentTAN JUN PIN·Filed 2011·Granted May 29, 2012·6 cites·17 claims
- 1275US7363526B1Method for transferring data across different clock domains with selectable delayALTERA CORP·Filed 2004·Granted Apr 22, 2008·21 cites·20 claims
- 1372US6599764B1Isolation testing scheme for multi-die packagesALTERA CORP·Filed 2001·Granted Jul 29, 2003·18 cites·20 claims
- 1469US9166591B1High speed IO bufferALTERA CORP·Filed 2013·Granted Oct 20, 2015·3 cites·17 claims
- 1568US9680773B1Integrated circuit with dynamically-adjustable buffer space for serial interfaceTAN ZUN YANG·Filed 2011·Granted Jun 13, 2017·4 cites·14 claims
- 1667US6605960B2Programmable logic configuration device with configuration memory accessible to a second deviceALTERA CORP·Filed 2002·Granted Aug 12, 2003·12 cites·21 claims
- 1760US8694944B1Predicting routability of integrated circuitsSOO SZE HUEY·Filed 2009·Granted Apr 8, 2014·4 cites·23 claims
- 1858US7639047B1Techniques for reducing clock skew in clock routing networksALTERA CORP·Filed 2008·Granted Dec 29, 2009·2 cites·20 claims
- 1958US7565390B1Circuitry for facilitating performance of multiply-accumulate operations in programmable logic devicesALTERA CORP·Filed 2005·Granted Jul 21, 2009·3 cites·26 claims
- 2058US7305640B1Programmable soft macro memory using gate array base cellsALTERA CORP·Filed 2004·Granted Dec 4, 2007·6 cites·31 claims
- 2157US7434192B2Techniques for optimizing design of a hard intellectual property block for data transmissionALTERA CORP·Filed 2004·Granted Oct 7, 2008·4 cites·15 claims
- 2256US8151224B1Method of designing integrated circuits including providing an option to select a mask layer setANG BOON JIN·Filed 2008·Granted Apr 3, 2012·2 cites·16 claims
- 2353US8400863B1Configurable memory blockTAN ZUN YANG·Filed 2010·Granted Mar 19, 2013·2 cites·20 claims
- 2452US9153572B1Integrated circuit system with dynamic decoupling and method of manufacture thereofALTERA CORP·Filed 2014·Granted Oct 6, 2015·0 cites·20 claims
- 2552US8686758B1Integrated circuit with configurable I/O transistor arrangementSIA KET CHIEW·Filed 2009·Granted Apr 1, 2014·3 cites·24 claims
- 2652US8659334B2Frequency control clock tuning circuitryLIM TEIK WAH·Filed 2012·Granted Feb 25, 2014·1 cites·20 claims
- 2752US8232823B1Frequency control clock tuning circuitryLIM TEIK WAH·Filed 2009·Granted Jul 31, 2012·3 cites·20 claims
- 2852US7843216B2Techniques for optimizing design of a hard intellectual property block for data transmissionALTERA CORP·Filed 2008·Granted Nov 30, 2010·0 cites·13 claims
- 2951US7233189B1Signal propagation circuitry for use on integrated circuitsALTERA CORP·Filed 2004·Granted Jun 19, 2007·2 cites·7 claims
- 3047US10339074B1Integrated circuit with dynamically-adjustable buffer space for serial interfaceALTERA CORP·Filed 2017·Granted Jul 2, 2019·0 cites·15 claims
- 3143US8739099B1Method and apparatus for determining clock uncertaintiesMARURI VICTOR R·Filed 2008·Granted May 27, 2014·0 cites·18 claims
- 3241US7479803B1Techniques for debugging hard intellectual property blocksALTERA CORP·Filed 2004·Granted Jan 20, 2009·4 cites·19 claims
- 3340US7787314B2Dynamic real-time delay characterization and configurationALTERA CORP·Filed 2008·Granted Aug 31, 2010·0 cites·18 claims
- 3440US7683689B1Delay circuit with delay cells in different orientationsALTERA CORP·Filed 2008·Granted Mar 23, 2010·0 cites·21 claims
- 3539US7218141B2Techniques for implementing hardwired decoders in differential input circuitsALTERA CORP·Filed 2004·Granted May 15, 2007·1 cites·21 claims
- 3633US8037444B1Programmable control of mask-programmable integrated circuit devicesALTERA CORP·Filed 2006·Granted Oct 11, 2011·0 cites·18 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →