Inventor · disambiguated record
Boaz Eitan
Also filed as: EITAN BOAZ
129 granted patents·19 pending applications·11,323 citations·filing 1981–2021
99Inventor score
Files withSAIFUN SEMICONDUCTORS LTD77WAFERSCALE INTEGRATION INC30EITAN BOAZ8EITAN MEDICAL LTD7Spansion Israel Ltd4
Top patents by PatentIndex Score
148 records- 0199US6552387B1Non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trappingSAIFUN SEMICONDUCTORS LTD·Filed 1998·Granted Apr 22, 2003·340 cites·15 claims
- 0299US6011725ATwo bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trappingSAIFUN SEMICONDUCTORS LTD·Filed 1999·Granted Jan 4, 2000·2.2k cites·16 claims
- 0399US5966603ANROM fabrication method with a periphery portionSAIFUN SEMICONDUCTORS LTD·Filed 1997·Granted Oct 12, 1999·451 cites·11 claims
- 0499US5768192ANon-volatile semiconductor memory cell utilizing asymmetrical charge trappingSAIFUN SEMICONDUCTORS LTD·Filed 1996·Granted Jun 16, 1998·1.8k cites·40 claims
- 0598US6566699B2Non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trappingSAIFUN SEMICONDUCTORS LTD·Filed 2001·Granted May 20, 2003·150 cites·8 claims
- 0698US6477084B2NROM cell with improved programming, erasing and cyclingSAIFUN SEMICONDUCTORS LTD·Filed 2001·Granted Nov 5, 2002·203 cites·4 claims
- 0798US6429063B1NROM cell with generally decoupled primary and secondary injectionSAIFUN SEMICONDUCTORS LTD·Filed 2000·Granted Aug 6, 2002·212 cites·30 claims
- 0898US6292394B1Method for programming of a semiconductor memory cellSAIFUN SEMICONDUCTORS LTD·Filed 2000·Granted Sep 18, 2001·199 cites·31 claims
- 0998US6215148B1NROM cell with improved programming, erasing and cyclingSAIFUN SEMICONDUCTORS LTD·Filed 1998·Granted Apr 10, 2001·280 cites·8 claims
- 1098US6134156AMethod for initiating a retrieval procedure in virtual ground arraysSAIFUN SEMICONDUCTORS LTD·Filed 1999·Granted Oct 17, 2000·223 cites·12 claims
- 1198US6030871AProcess for producing two bit ROM cell utilizing angled implantSAIFUN SEMICONDUCTORS LTD·Filed 1998·Granted Feb 29, 2000·324 cites·10 claims
- 1297US6768165B1Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trappingSAIFUN SEMICONDUCTORS LTD·Filed 1997·Granted Jul 27, 2004·128 cites·36 claims
- 1397US6649972B2Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trappingSAIFUN SEMICONDUCTORS LTD·Filed 2002·Granted Nov 18, 2003·83 cites·6 claims
- 1497US6643181B2Method for erasing a memory cellSAIFUN SEMICONDUCTORS LTD·Filed 2001·Granted Nov 4, 2003·147 cites·26 claims
- 1597US6490204B2Programming and erasing methods for a reference cell of an NROM arraySAIFUN SEMICONDUCTORS LTD·Filed 2001·Granted Dec 3, 2002·147 cites·16 claims
- 1697US6396741B1Programming of nonvolatile memory cellsSAIFUN SEMICONDUCTORS LTD·Filed 2000·Granted May 28, 2002·177 cites·43 claims
- 1797US6348711B1NROM cell with self-aligned programming and erasure areasSAIFUN SEMICONDUCTORS LTD·Filed 1999·Granted Feb 19, 2002·260 cites·4 claims
- 1897US6201282B1Two bit ROM cell and process for producing sameSAIFUN SEMICONDUCTORS LTD·Filed 1999·Granted Mar 13, 2001·255 cites·7 claims
- 1997US5963465ASymmetric segmented memory array architectureSAIFUN SEMICONDUCTORS LTD·Filed 1997·Granted Oct 5, 1999·141 cites·15 claims
- 2096US5204835AEprom virtual ground arrayWAFERSCALE INTEGRATION INC·Filed 1990·Granted Apr 20, 1993·146 cites·22 claims
- 2196US5042009AMethod for programming a floating gate memory deviceWAFERSCALE INTEGRATION INC·Filed 1988·Granted Aug 20, 1991·121 cites·30 claims
- 2296US4639893ASelf-aligned split gate EPROMWAFERSCALE INTEGRATION INC·Filed 1984·Granted Jan 27, 1987·77 cites·7 claims
- 2395US7116577B2Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trappingSAIFUN SEMICONDUCTORS LTD·Filed 2004·Granted Oct 3, 2006·51 cites·2 claims
- 2495US5796313ALow power programmable ring oscillatorWAFERSCALE INTEGRATION INC·Filed 1996·Granted Aug 18, 1998·124 cites·12 claims
- 2594US6928001B2Programming and erasing methods for a non-volatile memory cellSAIFUN SEMICONDUCTORS LTD·Filed 2000·Granted Aug 9, 2005·80 cites·14 claims
- 2694US6917544B2Multiple use memory chipSAIFUN SEMICONDUCTORS LTD·Filed 2002·Granted Jul 12, 2005·53 cites·34 claims
- 2794US6633496B2Symmetric architecture for memory cells having widely spread metal bit linesSAIFUN SEMICONDUCTORS LTD·Filed 2000·Granted Oct 14, 2003·71 cites·19 claims
- 2894US6535434B2Architecture and scheme for a non-strobed read sequenceSAIFUN SEMICONDUCTORS LTD·Filed 2001·Granted Mar 18, 2003·97 cites·46 claims
- 2994US6335874B1Symmetric segmented memory array architectureSAIFUN SEMICONDUCTORS LTD·Filed 2000·Granted Jan 1, 2002·68 cites·8 claims
- 3094US6128226AMethod and apparatus for operating with a close to ground signalSAIFUN SEMICONDUCTORS LTD·Filed 1999·Granted Oct 3, 2000·114 cites·9 claims
- 3193US6829172B2Programming of nonvolatile memory cellsSAIFUN SEMICONDUCTORS LTD·Filed 2002·Granted Dec 7, 2004·68 cites·41 claims
- 3293US6627555B2Method and circuit for minimizing the charging effect during manufacture of semiconductor devicesSAIFUN SEMICONDUCTORS LTD·Filed 2001·Granted Sep 30, 2003·63 cites·9 claims
- 3393US6584017B2Method for programming a reference cellSAIFUN SEMICONDUCTORS LTD·Filed 2001·Granted Jun 24, 2003·82 cites·24 claims
- 3493US5862076AFast EPROM arrayWAFERSCALE INTEGRATION INC·Filed 1992·Granted Jan 19, 1999·105 cites·33 claims
- 3593US5432730AElectrically programmable read only memory arrayWAFERSCALE INTEGRATION INC·Filed 1993·Granted Jul 11, 1995·108 cites·8 claims
- 3692US7808818B2Secondary injection for NROMSAIFUN SEMICONDUCTORS LTD·Filed 2006·Granted Oct 5, 2010·22 cites·31 claims
- 3792US7136304B2Method, system and circuit for programming a non-volatile memory arraySAIFUN SEMICONDUCTOR LTD·Filed 2003·Granted Nov 14, 2006·63 cites·17 claims
- 3892US7123532B2Operating array cells with matched reference cellsSAIFUN SEMICONDUCTORS LTD·Filed 2005·Granted Oct 17, 2006·21 cites·9 claims
- 3992US6937521B2Programming and erasing methods for a non-volatile memory cellSAIFUN SEMICONDUCTORS LTD·Filed 2002·Granted Aug 30, 2005·63 cites·8 claims
- 4092US6664588B2NROM cell with self-aligned programming and erasure areasSAIFUN SEMICONDUCTORS LTD·Filed 2001·Granted Dec 16, 2003·51 cites·9 claims
- 4192US6636440B2Method for operation of an EEPROM array, including refresh thereofSAIFUN SEMICONDUCTORS LTD·Filed 2001·Granted Oct 21, 2003·83 cites·36 claims
- 4292US6285574B1Symmetric segmented memory array architectureSAIFUN SEMICONDUCTORS LTD·Filed 1999·Granted Sep 4, 2001·80 cites·2 claims
- 4392US5568085AUnit for stabilizing voltage on a capacitive nodeWAFERSCALE INTEGRATION INC·Filed 1994·Granted Oct 22, 1996·71 cites·5 claims
- 4492US4649520ASingle layer polycrystalline floating gateWAFERSCALE INTEGRATION INC·Filed 1984·Granted Mar 10, 1987·63 cites·14 claims
- 4591US6700818B2Method for operating a memory deviceSAIFUN SEMICONDUCTORS LTD·Filed 2002·Granted Mar 2, 2004·51 cites·9 claims
- 4691US4758869ANonvolatile floating gate transistor structureWAFERSCALE INTEGRATION INC·Filed 1986·Granted Jul 19, 1988·70 cites·6 claims
- 4790US6885585B2NROM NOR arraySAIFUN SEMICONDUCTORS LTD·Filed 2001·Granted Apr 26, 2005·52 cites·14 claims
- 4890US6583007B1Reducing secondary injection effectsSAIFUN SEMICONDUCTORS LTD·Filed 2001·Granted Jun 24, 2003·53 cites·18 claims
- 4990US6133095AMethod for creating diffusion areas for sources and drains without an etch stepSAIFUN SEMICONDUCTORS LTD·Filed 1999·Granted Oct 17, 2000·83 cites·7 claims
- 5089US7638835B2Double density NROM with nitride strips (DDNS)SAIFUN SEMICONDUCTORS LTD·Filed 2006·Granted Dec 29, 2009·16 cites·3 claims
Showing the top 50 of 148 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →