Inventor · disambiguated record
Bodo Hoppe
Also filed as: HOPPE BODO · HOPPE BODO E · HOPPE BODO EBERHARD
20 granted patents·2 pending applications·54 citations·filing 2002–2023
92Inventor score
Top patents by PatentIndex Score
22 records- 0192US9443044B2Determining a quality parameter for a verification environmentIBM·Filed 2014·Granted Sep 13, 2016·21 cites·20 claims
- 0287US9483591B1Assuring chip reliability with automatic generation of drivers and assertionsIBM·Filed 2015·Granted Nov 1, 2016·6 cites·20 claims
- 0383US10318406B2Determine soft error resilience while verifying architectural complianceIBM·Filed 2017·Granted Jun 11, 2019·4 cites·20 claims
- 0476US9965580B2Ranking combinations of mutants, test cases and random seeds in mutation testingIBM·Filed 2015·Granted May 8, 2018·2 cites·19 claims
- 0569US9727754B2Protecting chip settings using secured scan chainsIBM·Filed 2015·Granted Aug 8, 2017·1 cites·20 claims
- 0669US9600616B1Assuring chip reliability with automatic generation of drivers and assertionsIBM·Filed 2016·Granted Mar 21, 2017·1 cites·20 claims
- 0769US7565636B2System for performing verification of logic circuitsIBM·Filed 2008·Granted Jul 21, 2009·4 cites·3 claims
- 0866US7398494B2Method for performing verification of logic circuitsIBM·Filed 2006·Granted Jul 8, 2008·3 cites·6 claims
- 0962US12188979B2Error protection analysis of an integrated circuitIBM·Filed 2023·Granted Jan 7, 2025·0 cites·20 claims
- 1057US9222973B2Protecting chip settings using secured scan chainsGEUKES BENEDIKT·Filed 2012·Granted Dec 29, 2015·1 cites·18 claims
- 1157US7213220B2Method for verification of gate level netlists using colored bitsIBM·Filed 2004·Granted May 1, 2007·6 cites·15 claims
- 1256US10896118B2Determine soft error resilience while verifying architectural complianceIBM·Filed 2019·Granted Jan 19, 2021·0 cites·20 claims
- 1356US10614192B2Ranking combinations of mutants, test cases and random seeds in mutation testingIBM·Filed 2018·Granted Apr 7, 2020·0 cites·19 claims
- 1454US7353159B2Method for parallel simulation on a single microprocessor using meta-modelsIBM·Filed 2002·Granted Apr 1, 2008·5 cites·5 claims
- 1553US11657159B2Identifying security vulnerabilities using modeled attribute propagationIBM·Filed 2020·Granted May 23, 2023·0 cites·17 claims
- 1652US9098653B2Verifying processor-sparing functionality in a simulation environmentIBM·Filed 2013·Granted Aug 4, 2015·0 cites·11 claims
- 1749US2025068814A1Instrumentation-assisted emulation debug of aspect-oriented hardware with mixed levels of abstractionIBM·Filed 2023·Application pending·0 cites
- 1847US11501047B2Error injection for timing margin protection and frequency closureIBM·Filed 2019·Granted Nov 15, 2022·0 cites·20 claims
- 1947US10430311B2Measuring execution time of benchmark programs in a simulated environmentIBM·Filed 2015·Granted Oct 1, 2019·0 cites·9 claims
- 2046US10437699B2Measuring execution time of benchmark programs in a simulated environmentIBM·Filed 2015·Granted Oct 8, 2019·0 cites·8 claims
- 2146US9015025B2Verifying processor-sparing functionality in a simulation environmentLETZ STEFAN·Filed 2011·Granted Apr 21, 2015·0 cites·18 claims
- 2243US2004230414A1Method for verification of hardware designs with multiple asynchronous frequency domainsIBM·Filed 2003·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →