Inventor · disambiguated record
Boh-Yi Huang
Also filed as: HUANG BOH-YI
10 granted patents·2 pending applications·17 citations·filing 2017–2025
84Inventor score
Technology areasG06F
Files withTAIWAN SEMICONDUCTOR MFG CO LTD12
Top patents by PatentIndex Score
12 records- 0193US11900037B2Circuit synthesis optimization for implements on integrated circuitTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Feb 13, 2024·2 cites·20 claims
- 0293US11403448B1Apparatus and method for mapping foundational components during design porting from one process technology to another process technologyTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Aug 2, 2022·7 cites·20 claims
- 0393US11347920B2Circuit synthesis optimization for implements on integrated circuitTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted May 31, 2022·3 cites·20 claims
- 0492US11783104B2Apparatus and method for mapping foundational components during design porting from one process technology to another process technologyTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Oct 10, 2023·3 cites·20 claims
- 0586US11620423B2Attribute-point-based timing constraint formal verificationTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Apr 4, 2023·2 cites·20 claims
- 0683US2025291989A1Circuit Synthesis Optimization for Implements on Integrated CircuitTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 0781US12340158B2Circuit synthesis optimization for implements on integrated circuitTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Granted Jun 24, 2025·0 cites·20 claims
- 0874US12169671B2Apparatus and method for mapping foundational components during design porting from one process technology to another process technologyTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Granted Dec 17, 2024·0 cites·20 claims
- 0973US11900035B2Attribute-point-based timing constraint formal verificationTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Granted Feb 13, 2024·0 cites·20 claims
- 1070US2025077751A1Systems and Methods for Generating Synthesizable Netlists From Register Transfer Level DesignsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Application pending·0 cites
- 1154US12175175B2Systems and methods for generating synthesizable netlists from register transfer level designsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Dec 24, 2024·0 cites·20 claims
- 1238US10540462B2Method and apparatus for speeding up gate-level simulationTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Jan 21, 2020·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →