Inventor · disambiguated record
Brian D. Barrick
Also filed as: BARRICK BRIAN · BARRICK BRIAN D · BARRICK BRIAN DAVID
88 granted patents·6 pending applications·235 citations·filing 2001–2022
99Inventor score
Top patents by PatentIndex Score
94 records- 0197US11249757B1Handling and fusing load instructions in a processorIBM·Filed 2020·Granted Feb 15, 2022·6 cites·18 claims
- 0295US11163571B1Fusion to enhance early address generation of load instructions in a microprocessorIBM·Filed 2020·Granted Nov 2, 2021·4 cites·20 claims
- 0391US9542233B1Managing a free list of resources to decrease control complexity and reduce power consumptionIBM·Filed 2016·Granted Jan 10, 2017·6 cites·1 claims
- 0489US11941398B1Fast mapper restore for flush in processorIBM·Filed 2022·Granted Mar 26, 2024·1 cites·20 claims
- 0587US11392386B2Program counter (PC)-relative load and store addressing for fused instructionsIBM·Filed 2020·Granted Jul 19, 2022·2 cites·20 claims
- 0687US9928128B2In-pipe error scrubbing within a processor coreIBM·Filed 2016·Granted Mar 27, 2018·6 cites·15 claims
- 0786US7302527B2Systems and methods for executing load instructions that avoid order violationsIBM·Filed 2004·Granted Nov 27, 2007·47 cites·32 claims
- 0884US11868773B2Inferring future value for speculative branch resolution in a microprocessorIBM·Filed 2022·Granted Jan 9, 2024·1 cites·20 claims
- 0983US11531548B1Fast perfect issue of dependent instructions in a distributed issue queue systemIBM·Filed 2021·Granted Dec 20, 2022·1 cites·20 claims
- 1083US11119772B2Check pointing of accumulator register results in a microprocessorIBM·Filed 2019·Granted Sep 14, 2021·3 cites·18 claims
- 1181US10248426B2Direct register restore mechanism for distributed history buffersIBM·Filed 2016·Granted Apr 2, 2019·3 cites·17 claims
- 1281US8661230B2Allocation of counters from a pool of counters to track mappings of logical registers to physical registers for mapper based instruction executionsALEXANDER GREGORY W·Filed 2011·Granted Feb 25, 2014·5 cites·7 claims
- 1381US6578130B2Programmable data prefetch pacingIBM·Filed 2001·Granted Jun 10, 2003·35 cites·19 claims
- 1480US10949213B2Logical register recovery within a processorIBM·Filed 2018·Granted Mar 16, 2021·2 cites·20 claims
- 1579US10353817B2Cache miss thread balancingIBM·Filed 2017·Granted Jul 16, 2019·2 cites·23 claims
- 1679US9069546B2Allocation of counters from a pool of counters to track mappings of logical registers to physical registers for mapper based instruction executionsALEXANDER GREGORY W·Filed 2012·Granted Jun 30, 2015·4 cites·7 claims
- 1779US7769984B2Dual-issuance of microprocessor instructions using dual dependency matricesIBM·Filed 2008·Granted Aug 3, 2010·9 cites·1 claims
- 1878US10007526B2Freelist based global completion table having both thread-specific and global completion table identifiersIBM·Filed 2015·Granted Jun 26, 2018·2 cites·11 claims
- 1978US8627047B2Store data forwarding with no memory model restrictionsTSAI AARON·Filed 2008·Granted Jan 7, 2014·8 cites·10 claims
- 2076US7953932B2System and method for avoiding deadlocks when performing storage updates in a multi-processor environmentIBM·Filed 2008·Granted May 31, 2011·7 cites·20 claims
- 2175US8683180B2Intermediate register mapperBARRICK BRIAN D·Filed 2009·Granted Mar 25, 2014·8 cites·21 claims
- 2273US11995445B2Assignment of microprocessor register tags at issue timeIBM·Filed 2022·Granted May 28, 2024·0 cites·25 claims
- 2373US10268482B2Multi-slice processor issue of a dependent instruction in an issue queue based on issue of a producer instructionIBM·Filed 2015·Granted Apr 23, 2019·2 cites·10 claims
- 2472US10379867B2Asynchronous flush and restore of distributed history bufferIBM·Filed 2017·Granted Aug 13, 2019·1 cites·20 claims
- 2572US7464242B2Method of load/store dependencies detection with dynamically changing address lengthIBM·Filed 2005·Granted Dec 9, 2008·6 cites·14 claims
- 2671US11144364B2Supporting speculative microprocessor instruction executionIBM·Filed 2019·Granted Oct 12, 2021·1 cites·18 claims
- 2770US10592422B2Data-less history buffer with banked restore ports in a register mapperIBM·Filed 2017·Granted Mar 17, 2020·1 cites·19 claims
- 2869US10545765B2Multi-level history buffer for transaction memory in a microprocessorIBM·Filed 2017·Granted Jan 28, 2020·1 cites·20 claims
- 2967US10719056B2Merging status and control data in a reservation stationIBM·Filed 2016·Granted Jul 21, 2020·1 cites·20 claims
- 3066US10007525B2Freelist based global completion table having both thread-specific and global completion table identifiersIBM·Filed 2014·Granted Jun 26, 2018·1 cites·20 claims
- 3164US11500642B2Assignment of microprocessor register tags at issue timeIBM·Filed 2020·Granted Nov 15, 2022·0 cites·20 claims
- 3264US11360775B2Slice-based allocation history bufferIBM·Filed 2020·Granted Jun 14, 2022·0 cites·20 claims
- 3364US11360779B2Logical register recovery within a processorIBM·Filed 2020·Granted Jun 14, 2022·0 cites·20 claims
- 3464US7376816B2Method and systems for executing load instructions that achieve sequential load consistencyIBM·Filed 2004·Granted May 20, 2008·8 cites·7 claims
- 3563US7904697B2Load register instruction short circuiting methodIBM·Filed 2008·Granted Mar 8, 2011·2 cites·17 claims
- 3663US7769985B2Load address dependency mechanism system and method in a high frequency, low power processor systemIBM·Filed 2008·Granted Aug 3, 2010·2 cites·9 claims
- 3763US7730290B2Systems for executing load instructions that achieve sequential load consistencyIBM·Filed 2008·Granted Jun 1, 2010·2 cites·13 claims
- 3863US6895454B2Method and apparatus for sharing resources between different queue typesIBM·Filed 2001·Granted May 17, 2005·9 cites·9 claims
- 3962US7302530B2Method of updating cache state information where stores only read the cache state information upon entering the queueIBM·Filed 2004·Granted Nov 27, 2007·8 cites·26 claims
- 4061US11327757B2Processor providing intelligent management of values buffered in overlaid architected and non-architected register filesIBM·Filed 2020·Granted May 10, 2022·0 cites·20 claims
- 4161US11138050B2Operation of a multi-slice processor implementing a hardware level transfer of an execution threadIBM·Filed 2019·Granted Oct 5, 2021·0 cites·20 claims
- 4261US10963380B2Cache miss thread balancingIBM·Filed 2019·Granted Mar 30, 2021·0 cites·18 claims
- 4360US10140127B2Operation of a multi-slice processor with selective producer instruction typesIBM·Filed 2018·Granted Nov 27, 2018·0 cites·13 claims
- 4460US10127047B2Operation of a multi-slice processor with selective producer instruction typesIBM·Filed 2018·Granted Nov 13, 2018·0 cites·7 claims
- 4560US7177982B2Method to maintain order between multiple queues with different ordering requirements in a high frequency systemIBM·Filed 2004·Granted Feb 13, 2007·9 cites·14 claims
- 4658US11886883B2Dependency skipping in a load-compare-jump sequence of instructions by incorporating compare functionality into the jump instruction and auto-finishing the compare instructionIBM·Filed 2021·Granted Jan 30, 2024·0 cites·20 claims
- 4758US10884752B2Slice-based allocation history bufferIBM·Filed 2017·Granted Jan 5, 2021·0 cites·20 claims
- 4857US11537402B1Execution elision of intermediate instruction by processorIBM·Filed 2021·Granted Dec 27, 2022·0 cites·20 claims
- 4957US9703614B2Managing a free list of resources to decrease control complexity and reduce power consumptionIBM·Filed 2016·Granted Jul 11, 2017·0 cites·1 claims
- 5057US7152152B2Method of avoiding flush due to store queue full in a high frequency system with a stall mechanism and no reject mechanismIBM·Filed 2004·Granted Dec 19, 2006·7 cites·12 claims
Showing the top 50 of 94 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →