Inventor · disambiguated record
Brad B. Beavers
Also filed as: BEAVERS BRAD · BEAVERS BRAD B
4 granted patents·123 citations·filing 1994–1996
80Inventor score
Technology areasG06F
Top patents by PatentIndex Score
4 records- 0160US5835946AHigh performance implementation of the load reserve instruction in a superscalar microprocessor that supports multi-level cache organizationsIBM·Filed 1996·Granted Nov 10, 1998·42 cites·7 claims
- 0254US5682495AFully associative address translation buffer having separate segment and page invalidationIBM·Filed 1994·Granted Oct 28, 1997·28 cites·6 claims
- 0352US5604879ASingle array address translator with segment and page invalidate ability and method of operationMOTOROLA INC·Filed 1996·Granted Feb 18, 1997·33 cites·4 claims
- 0447US5530822AAddress translator and method of operationMOTOROLA INC·Filed 1994·Granted Jun 25, 1996·20 cites·10 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →