Inventor · disambiguated record
Brett W. Coon
Also filed as: COON BRETT · COON BRETT W
89 granted patents·3 pending applications·2,364 citations·filing 1992–2024
99Inventor score
Top patents by PatentIndex Score
92 records- 0198US7788468B1Synchronization of threads in a cooperative thread arrayNVIDIA CORP·Filed 2005·Granted Aug 31, 2010·169 cites·18 claims
- 0298US7353369B1System and method for managing divergent threads in a SIMD architectureNVIDIA CORP·Filed 2005·Granted Apr 1, 2008·96 cites·15 claims
- 0397US7680988B1Single interconnect providing read and write access to a memory shared by concurrent threadsNVIDIA CORP·Filed 2006·Granted Mar 16, 2010·101 cites·21 claims
- 0497US7617384B1Structured programming control flow using a disable mask in a SIMD architectureNVIDIA CORP·Filed 2007·Granted Nov 10, 2009·83 cites·20 claims
- 0596US8327123B2Maximized memory throughput on parallel processing devicesJUFFA NORBERT·Filed 2011·Granted Dec 4, 2012·40 cites·20 claims
- 0696US8108625B1Shared memory with parallel access and access conflict resolution mechanismCOON BRETT W·Filed 2006·Granted Jan 31, 2012·73 cites·19 claims
- 0796US8074224B1Managing state information for a multi-threaded processorNORDQUIST BRYON S·Filed 2005·Granted Dec 6, 2011·89 cites·13 claims
- 0896US7925860B1Maximized memory throughput using cooperative thread arraysNVIDIA CORP·Filed 2007·Granted Apr 12, 2011·48 cites·16 claims
- 0996US7434032B1Tracking register usage during multithreaded processing using a scoreboard having separate memory regions and storing sequential register size indicatorsNVIDIA CORP·Filed 2005·Granted Oct 7, 2008·52 cites·13 claims
- 1096US7366878B1Scheduling instructions from multi-thread instruction buffer based on phase boundary qualifying rule for phases of math and data access operations with better cachingNVIDIA CORP·Filed 2006·Granted Apr 29, 2008·47 cites·20 claims
- 1195US7877585B1Structured programming control flow in a SIMD architectureNVIDIA CORP·Filed 2007·Granted Jan 25, 2011·47 cites·20 claims
- 1295US7761697B1Processing an indirect branch instruction in a SIMD architectureNVIDIA CORP·Filed 2006·Granted Jul 20, 2010·52 cites·20 claims
- 1395US7676657B2Across-thread out-of-order instruction dispatch in a multithreaded microprocessorNVIDIA CORP·Filed 2006·Granted Mar 9, 2010·35 cites·19 claims
- 1495US7634621B1Register file allocationNVIDIA CORP·Filed 2006·Granted Dec 15, 2009·45 cites·24 claims
- 1595US7600155B1Apparatus and method for monitoring and debugging a graphics processing unitNVIDIA CORP·Filed 2005·Granted Oct 6, 2009·51 cites·20 claims
- 1695US7543136B1System and method for managing divergent threads using synchronization tokens and program instructions that include set-synchronization bitsNVIDIA CORP·Filed 2005·Granted Jun 2, 2009·45 cites·19 claims
- 1795US5438668ASystem and method for extraction, alignment and decoding of CISC instructions into a nano-instruction bucket for execution by a RISC computerSEIKO EPSON CORP·Filed 1992·Granted Aug 1, 1995·159 cites·29 claims
- 1894US8117423B1Pipeline replay support for multicycle operationsCOON BRETT·Filed 2008·Granted Feb 14, 2012·34 cites·20 claims
- 1994US7711990B1Apparatus and method for debugging a graphics processing unit in response to a debug instructionNVIDIA CORP·Filed 2005·Granted May 4, 2010·42 cites·17 claims
- 2094US7644210B1Method and system for storing and retrieving a translation of target program instruction from a host processor using fast look-up of indirect branch destination in a dynamic translation systemBANNING JOHN·Filed 2006·Granted Jan 5, 2010·49 cites·46 claims
- 2193US10866305B1Signal processing for near-field radarWAYMO LLC·Filed 2018·Granted Dec 15, 2020·10 cites·19 claims
- 2292US8176265B2Shared single-access memory with management of multiple parallel requestsCOON BRETT W·Filed 2011·Granted May 8, 2012·16 cites·8 claims
- 2391US7542043B1Subdividing a shader programNVIDIA CORP·Filed 2005·Granted Jun 2, 2009·24 cites·17 claims
- 2490US10365930B2Instructions for managing a parallel cache hierarchyNVIDIA CORP·Filed 2017·Granted Jul 30, 2019·5 cites·14 claims
- 2590US8732713B2Thread group scheduler for computing on a parallel thread processorCOON BRETT W·Filed 2011·Granted May 20, 2014·15 cites·20 claims
- 2690US7834881B2Operand collector architectureNVIDIA CORP·Filed 2006·Granted Nov 16, 2010·22 cites·20 claims
- 2790US5619666ASystem for translating non-native instructions to native instructions and combining them into a final bucket for processing on a host processorSEIKO EPSON CORP·Filed 1995·Granted Apr 8, 1997·110 cites·12 claims
- 2889US9952977B2Cache operations and policies for a multi-threaded clientHEINRICH STEVEN JAMES·Filed 2010·Granted Apr 24, 2018·21 cites·25 claims
- 2989US8174531B1Programmable graphics processor for multithreaded execution of programsLINDHOLM JOHN ERIK·Filed 2009·Granted May 8, 2012·16 cites·10 claims
- 3089US7111096B1Fast look-up of indirect branch destination in a dynamic translation systemTRANSMETA CORP·Filed 2003·Granted Sep 19, 2006·52 cites·30 claims
- 3188US8055856B2Lock mechanism to enable atomic updates to shared memoryNVIDIA CORP·Filed 2008·Granted Nov 8, 2011·16 cites·18 claims
- 3288US7949855B1Scheduler in multi-threaded processor prioritizing instructions passing qualification ruleNVIDIA CORP·Filed 2008·Granted May 24, 2011·15 cites·20 claims
- 3387US7418576B1Prioritized issuing of operation dedicated execution unit tagged instructions from multiple different type threads performing different set of operationsNVIDIA CORP·Filed 2004·Granted Aug 26, 2008·36 cites·20 claims
- 3487US5546552AMethod for translating non-native instructions to native instructions and combining them into a final bucket for processing on a host processorSEIKO EPSON CORP·Filed 1995·Granted Aug 13, 1996·82 cites·7 claims
- 3586US12504507B2Signal processing for near-field radarWAYMO LLC·Filed 2024·Granted Dec 23, 2025·0 cites·20 claims
- 3686US8095829B1Soldier-on mode to control processor error handling behaviorCOON BRETT W·Filed 2007·Granted Jan 10, 2012·16 cites·20 claims
- 3786US6615300B1Fast look-up of indirect branch destination in a dynamic translation systemTRANSMETA CORP·Filed 2000·Granted Sep 2, 2003·42 cites·15 claims
- 3885US9639365B2Indirect function call instructions in a synchronous parallel thread processorNVIDIA CORP·Filed 2012·Granted May 2, 2017·7 cites·22 claims
- 3985US8751771B2Efficient implementation of arrays of structures on SIMT and SIMD architecturesFAHS BRIAN·Filed 2011·Granted Jun 10, 2014·9 cites·20 claims
- 4085US8405665B2Programmable graphics processor for multithreaded execution of programsLINDHOLM JOHN ERIK·Filed 2012·Granted Mar 26, 2013·7 cites·15 claims
- 4184US9223578B2Coalescing memory barrier operations across multiple parallel threadsNICKOLLS JOHN R·Filed 2010·Granted Dec 29, 2015·8 cites·21 claims
- 4284US8312254B2Indirect function call instructions in a synchronous parallel thread processorCOON BRETT W·Filed 2008·Granted Nov 13, 2012·11 cites·16 claims
- 4383US6738892B1Use of enable bits to control execution of selected instructionsTRANSMETA CORP·Filed 1999·Granted May 18, 2004·106 cites·15 claims
- 4482US2025085389A1Dynamic Loading of Radar Unit Configuration Data Based on Changing Radar ParametersWAYMO LLC·Filed 2024·Application pending·0 cites
- 4581US9830197B2Cooperative thread array reduction and scan operationsNVIDIA CORP·Filed 2016·Granted Nov 28, 2017·2 cites·20 claims
- 4681US9659339B2Programmable graphics processor for multithreaded execution of programsNVIDIA CORP·Filed 2013·Granted May 23, 2017·5 cites·23 claims
- 4781US8375176B2Lock mechanism to enable atomic updates to shared memoryNVIDIA CORP·Filed 2011·Granted Feb 12, 2013·5 cites·17 claims
- 4881US7664935B2System and method for translating non-native instructions to native instructions for processing on a host processorCOON BRETT·Filed 2008·Granted Feb 16, 2010·6 cites·18 claims
- 4980US12196883B2Dynamic loading of radar unit configuration data based on changing radar parametersWAYMO LLC·Filed 2023·Granted Jan 14, 2025·0 cites·20 claims
- 5080US7805573B1Multi-threaded stack cacheNVIDIA CORP·Filed 2005·Granted Sep 28, 2010·10 cites·19 claims
Showing the top 50 of 92 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →