Inventor · disambiguated record
Bradly G. Frey
Also filed as: FREY BRADLY G · FREY BRADLY GEORGE
54 granted patents·5 pending applications·629 citations·filing 1989–2023
98Inventor score
Top patents by PatentIndex Score
59 records- 0196US10067713B2Efficient enforcement of barriers with respect to memory move sequencesIBM·Filed 2016·Granted Sep 4, 2018·17 cites·19 claims
- 0296US9785557B1Translation entry invalidation in a multithreaded data processing systemIBM·Filed 2016·Granted Oct 10, 2017·23 cites·20 claims
- 0393US10387686B2Hardware based isolation for secure execution of virtual machinesIBM·Filed 2017·Granted Aug 20, 2019·11 cites·24 claims
- 0493US7904661B2Data stream prefetching in a microprocessorIBM·Filed 2007·Granted Mar 8, 2011·32 cites·13 claims
- 0592US9323692B2Managing translation of a same address across multiple contexts using a same entry in a translation lookaside bufferIBM·Filed 2014·Granted Apr 26, 2016·15 cites·13 claims
- 0692US9317443B2Managing translations across multiple contexts using a TLB with entries directed to multiple privilege levels and to multiple types of address spacesIBM·Filed 2014·Granted Apr 19, 2016·17 cites·12 claims
- 0792US8544022B2Transactional memory preemption mechanismARNDT RICHARD L·Filed 2012·Granted Sep 24, 2013·17 cites·5 claims
- 0891US9772945B1Translation entry invalidation in a multithreaded data processing systemIBM·Filed 2016·Granted Sep 26, 2017·9 cites·20 claims
- 0991US5185871ACoordination of out-of-sequence fetching between multiple processors using re-execution of instructionsIBM·Filed 1989·Granted Feb 9, 1993·141 cites·38 claims
- 1090US11797713B2Systems and methods for dynamic control of a secure mode of operation in a processorIBM·Filed 2020·Granted Oct 24, 2023·2 cites·24 claims
- 1190US7350029B2Data stream prefetching in a microprocessorIBM·Filed 2005·Granted Mar 25, 2008·22 cites·7 claims
- 1289US8615644B2Processor with hardware thread control logic indicating disable status when instructions accessing shared resources are completed for safe shared resource conditionBRUCE BECKY·Filed 2010·Granted Dec 24, 2013·18 cites·13 claims
- 1385US9430166B2Interaction of transactional storage accesses with other atomic semanticsIBM·Filed 2012·Granted Aug 30, 2016·6 cites·26 claims
- 1484US9575825B2Push instruction for pushing a message payload from a sending thread to a receiving threadIBM·Filed 2014·Granted Feb 21, 2017·6 cites·10 claims
- 1584US9047079B2Indicating disabled thread to other threads when contending instructions complete execution to ensure safe shared resource conditionBRUCE BECKY·Filed 2012·Granted Jun 2, 2015·10 cites·7 claims
- 1683US10817434B2Interruptible translation entry invalidation in a multithreaded data processing systemIBM·Filed 2018·Granted Oct 27, 2020·3 cites·16 claims
- 1781US8140759B2Specifying an access hint for prefetching partial cache block data in a cache hierarchyFREY BRADLY GEORGE·Filed 2009·Granted Mar 20, 2012·12 cites·20 claims
- 1880US8424015B2Transactional memory preemption mechanismARNDT RICHARD L·Filed 2010·Granted Apr 16, 2013·5 cites·10 claims
- 1979US9330023B2Managing translations across multiple contexts using a TLB with entries directed to multiple privilege levels and to multiple types of address spacesIBM·Filed 2014·Granted May 3, 2016·4 cites·8 claims
- 2079US5835738AAddress space architecture for multiple bus computer systemsIBM·Filed 1996·Granted Nov 10, 1998·118 cites·18 claims
- 2178US9600419B2Selectable address translation mechanismsIBM·Filed 2012·Granted Mar 21, 2017·4 cites·20 claims
- 2277US7908457B2Retaining an association between a virtual address based buffer and a user space application that owns the bufferIBM·Filed 2008·Granted Mar 15, 2011·8 cites·11 claims
- 2376US12223098B2Systems and methods for dynamic control of a secure mode of operation in a processorIBM·Filed 2023·Granted Feb 11, 2025·0 cites·20 claims
- 2473US11226902B2Translation load instruction with access protectionIBM·Filed 2019·Granted Jan 18, 2022·1 cites·22 claims
- 2571US5533205AMethod and system for efficient bus allocation in a multimedia computer systemIBM·Filed 1994·Granted Jul 2, 1996·54 cites·6 claims
- 2670US6338119B1Method and apparatus with page buffer and I/O page kill definition for improved DMA and L1/L2 cache performanceIBM·Filed 1999·Granted Jan 8, 2002·55 cites·9 claims
- 2768US9396115B2Rewind only transactions in a data processing system supporting transactional storage accessesIBM·Filed 2012·Granted Jul 19, 2016·2 cites·21 claims
- 2868US9251088B2Mechanisms for eliminating a race condition between a hypervisor-performed emulation process requiring a translation operation and a concurrent translation table entry invalidationIBM·Filed 2013·Granted Feb 2, 2016·2 cites·20 claims
- 2967US10152322B2Memory move instruction sequence including a stream of copy-type and paste-type instructionsIBM·Filed 2016·Granted Dec 11, 2018·1 cites·18 claims
- 3067US8589657B2Operating system management of address-translation-related data structures and hardware lookasidesFREY BRADLY GEORGE·Filed 2011·Granted Nov 19, 2013·2 cites·14 claims
- 3166US9626187B2Transactional memory system supporting unbroken suspended executionCAIN III HAROLD W·Filed 2010·Granted Apr 18, 2017·2 cites·21 claims
- 3266US9244846B2Ensuring causality of transactional storage accesses interacting with non-transactional storage accessesFREY BRADLY G·Filed 2012·Granted Jan 26, 2016·2 cites·25 claims
- 3366US7827343B2Method and apparatus for providing accelerator support in a bus protocolIBM·Filed 2007·Granted Nov 2, 2010·3 cites·17 claims
- 3465US9367264B2Transaction check instruction for memory transactionsIBM·Filed 2013·Granted Jun 14, 2016·1 cites·6 claims
- 3565US9311249B2Managing translation of a same address across multiple contexts using a same entry in a translation lookaside bufferIBM·Filed 2014·Granted Apr 12, 2016·1 cites·7 claims
- 3664US10956340B2Hardware-based pre-page walk virtual address transformation independent of page size utilizing bit shifting based on page sizeIBM·Filed 2019·Granted Mar 23, 2021·0 cites·6 claims
- 3762US9747212B2Virtual unifed instruction and data caches including storing program instructions and memory address in CAM indicated by store instruction containing bit directly indicating self modifying codeIBM·Filed 2013·Granted Aug 29, 2017·1 cites·15 claims
- 3860US11119932B2Operation of a multi-slice processor implementing adaptive prefetch controlIBM·Filed 2019·Granted Sep 14, 2021·0 cites·20 claims
- 3958US10613792B2Efficient enforcement of barriers with respect to memory move sequencesIBM·Filed 2018·Granted Apr 7, 2020·0 cites·19 claims
- 4058US9619345B2Apparatus for determining failure context in hardware transactional memoriesCAIN HAROLD W·Filed 2012·Granted Apr 11, 2017·1 cites·16 claims
- 4156US8856453B2Persistent prefetch data stream settingsDALE JASON N·Filed 2012·Granted Oct 7, 2014·1 cites·20 claims
- 4255US10331566B2Operation of a multi-slice processor implementing adaptive prefetch controlIBM·Filed 2016·Granted Jun 25, 2019·0 cites·20 claims
- 4355US10216642B2Hardware-based pre-page walk virtual address transformation where the virtual address is shifted by current page size and a minimum page sizeIBM·Filed 2013·Granted Feb 26, 2019·0 cites·15 claims
- 4455US2014281209A1Hardware-based pre-page walk virtual address transformationIBM·Filed 2013·Application pending·0 cites
- 4554US9367263B2Transaction check instruction for memory transactionsIBM·Filed 2012·Granted Jun 14, 2016·0 cites·15 claims
- 4653US9626256B2Determining failure context in hardware transactional memoriesIBM·Filed 2013·Granted Apr 18, 2017·0 cites·8 claims
- 4752US2014101407A1Selectable address translation mechanismsIBM·Filed 2013·Application pending·0 cites
- 4851US9569293B2Push instruction for pushing a message payload from a sending thread to a receiving threadIBM·Filed 2015·Granted Feb 14, 2017·0 cites·5 claims
- 4951US9268598B2Recording and profiling transaction failure source addresses and states of validity indicator corresponding to addresses of aborted transaction in hardware transactional memoriesBLAINEY ROBERT J·Filed 2012·Granted Feb 23, 2016·0 cites·10 claims
- 5051US8645667B2Operating system management of address-translation-related data structures and hardware lookasidesFREY BRADLY GEORGE·Filed 2012·Granted Feb 4, 2014·0 cites·8 claims
Showing the top 50 of 59 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →