Inventor · disambiguated record
Brad J. Garni
Also filed as: GARNI BRAD · GARNI BRAD J · GARNI BRAD JOHN
12 granted patents·130 citations·filing 2002–2020
90Inventor score
Top patents by PatentIndex Score
12 records- 0196US11233663B1Physically unclonable function having source bias transistorsNXP USA INC·Filed 2020·Granted Jan 25, 2022·11 cites·20 claims
- 0294US10574469B1Physically unclonable function and method for generating a digital codeNXP USA INC·Filed 2019·Granted Feb 25, 2020·17 cites·13 claims
- 0388US8995178B1SRAM with embedded ROMYANG JIANAN·Filed 2013·Granted Mar 31, 2015·8 cites·20 claims
- 0484US6711068B2Balanced load memory and method of operationMOTOROLA INC·Filed 2002·Granted Mar 23, 2004·38 cites·22 claims
- 0582US8685800B2Single event latch-up prevention techniques for a semiconductor deviceYANG JIANAN·Filed 2012·Granted Apr 1, 2014·6 cites·15 claims
- 0680US11056161B2Data processing system and method for generating a digital code with a physically unclonable functionNXP USA INC·Filed 2019·Granted Jul 6, 2021·3 cites·18 claims
- 0776US6693824B2Circuit and method of writing a toggle memoryMOTOROLA INC·Filed 2002·Granted Feb 17, 2004·23 cites·19 claims
- 0871US6744663B2Circuit and method for reading a toggle memory cellMOTOROLA INC·Filed 2002·Granted Jun 1, 2004·19 cites·24 claims
- 0962US7292484B1Sense amplifier with multiple bits sharing a common referenceFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Nov 6, 2007·5 cites·20 claims
- 1049US9123545B2Semiconductor device with single-event latch-up prevention circuitryYANG JIANAN·Filed 2014·Granted Sep 1, 2015·0 cites·18 claims
- 1140US10453544B2Memory array with read only cells having multiple states and method of programming thereofFREESCALE SEMICONDUCTOR INC·Filed 2014·Granted Oct 22, 2019·0 cites·17 claims
- 1234US7881138B2Memory circuit with sense amplifierFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Feb 1, 2011·0 cites·18 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →