Inventor · disambiguated record
Bruce M. Gilbert
Also filed as: GILBERT BRUCE M · GILBERT BRUCE MICHAEL
20 granted patents·531 citations·filing 1996–2008
96Inventor score
Technology areasG06F
Top patents by PatentIndex Score
20 records- 0192US7124410B2Distributed allocation of system hardware resources for multiprocessor systemsIBM·Filed 2002·Granted Oct 17, 2006·95 cites·18 claims
- 0286US6598120B1Assignment of building block collector agent to receive acknowledgments from other building block agentsIBM·Filed 2002·Granted Jul 22, 2003·47 cites·20 claims
- 0383US7051180B2Masterless building block binding to partitions using identifiers and indicatorsIBM·Filed 2002·Granted May 23, 2006·38 cites·27 claims
- 0479US6910108B2Hardware support for partitioning a multiprocessor system to allow distinct operating systemsIBM·Filed 2002·Granted Jun 21, 2005·28 cites·14 claims
- 0576US6295584B1Multiprocessor computer system with memory map translationIBM·Filed 1997·Granted Sep 25, 2001·79 cites·14 claims
- 0676US5900020AMethod and apparatus for maintaining an order of write operations by processors in a multiprocessor computer to maintain memory consistencySEQUENT COMPUTER SYSTEMS INC·Filed 1996·Granted May 4, 1999·79 cites·23 claims
- 0769US8578130B2Partitioning of node into more than one partitionDESOTA DONALD R·Filed 2003·Granted Nov 5, 2013·17 cites·14 claims
- 0868US6591370B1Multinode computer system with distributed clock synchronization systemIBM·Filed 1999·Granted Jul 8, 2003·50 cites·33 claims
- 0965US6973544B2Method and apparatus of using global snooping to provide cache coherence to distributed computer nodes in a single coherent systemIBM·Filed 2002·Granted Dec 6, 2005·11 cites·9 claims
- 1063US7827449B2Non-inline transaction error correctionIBM·Filed 2008·Granted Nov 2, 2010·2 cites·10 claims
- 1160US7383464B2Non-inline transaction error correctionIBM·Filed 2003·Granted Jun 3, 2008·6 cites·6 claims
- 1256US6996665B2Hazard queue for transaction pipelineIBM·Filed 2002·Granted Feb 7, 2006·4 cites·18 claims
- 1355US6996675B2Retrieval of all tag entries of cache locations for memory address and determining ECC based on sameIBM·Filed 2002·Granted Feb 7, 2006·4 cites·19 claims
- 1454US7210018B2Multiple-stage pipeline for transaction conversionIBM·Filed 2002·Granted Apr 24, 2007·3 cites·19 claims
- 1553US8250330B2Memory controller having tables mapping memory addresses to memory modulesLAIS ERIC N·Filed 2004·Granted Aug 21, 2012·3 cites·5 claims
- 1653US6636944B1Associative cache and method for replacing data entries having an IO stateIBM·Filed 1997·Granted Oct 21, 2003·29 cites·20 claims
- 1753US6041376ADistributed shared memory system having a first node that prevents other nodes from accessing requested data until a processor on the first node controls the requested dataSEQUENT COMPUTER SYSTEMS INC·Filed 1997·Granted Mar 21, 2000·29 cites·23 claims
- 1852US7000089B2Address assignment to transaction for serializationIBM·Filed 2002·Granted Feb 14, 2006·4 cites·20 claims
- 1952US6823498B2Masterless building block binding to partitionsIBM·Filed 2002·Granted Nov 23, 2004·3 cites·20 claims
- 2042US6934835B2Building block removal from partitionsIBM·Filed 2002·Granted Aug 23, 2005·0 cites·21 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →