Inventor · disambiguated record
Brett Olsson
Also filed as: OLSSON BRETT
70 granted patents·9 pending applications·2,071 citations·filing 1994–2021
99Inventor score
Technology areasG06F
Top patents by PatentIndex Score
79 records- 0197US9727337B2Fine-grained instruction enablement at sub-function granularity based on an indicated subrange of registersIBM·Filed 2012·Granted Aug 8, 2017·48 cites·10 claims
- 0296US7877582B2Multi-addressable register fileIBM·Filed 2008·Granted Jan 25, 2011·68 cites·19 claims
- 0396US5513366AMethod and system for dynamically reconfiguring a register file in a vector processorIBM·Filed 1994·Granted Apr 30, 1996·311 cites·7 claims
- 0495US7793081B2Implementing instruction set architectures with non-contiguous register file specifiersIBM·Filed 2008·Granted Sep 7, 2010·34 cites·5 claims
- 0595US7421566B2Implementing instruction set architectures with non-contiguous register file specifiersIBM·Filed 2006·Granted Sep 2, 2008·38 cites·1 claims
- 0695US5887183AMethod and system in a data processing system for loading and storing vectors in a plurality of modesIBM·Filed 1995·Granted Mar 23, 1999·315 cites·3 claims
- 0794US8166281B2Implementing instruction set architectures with non-contiguous register file specifiersGSCHWIND MICHAEL KARL·Filed 2009·Granted Apr 24, 2012·30 cites·16 claims
- 0893US8918623B2Implementing instruction set architectures with non-contiguous register file specifiersGSCHWIND MICHAEL KARL·Filed 2012·Granted Dec 23, 2014·23 cites·18 claims
- 0992US8458442B2Method and structure of using SIMD vector architectures to implement matrix multiplicationEICHENBERGER ALEXANDRE E·Filed 2009·Granted Jun 4, 2013·30 cites·24 claims
- 1090US9785435B1Floating point instruction with selectable comparison attributesIBM·Filed 2016·Granted Oct 10, 2017·7 cites·20 claims
- 1190US9395981B2Multi-addressable register files and format conversions associated therewithIBM·Filed 2012·Granted Jul 19, 2016·11 cites·10 claims
- 1289US5758176AMethod and system for providing a single-instruction, multiple-data execution unit for performing single-instruction, multiple-data operations within a superscalar data processing systemIBM·Filed 1994·Granted May 26, 1998·148 cites·11 claims
- 1388US9727353B2Simultaneously capturing status information for multiple operating modesIBM·Filed 2015·Granted Aug 8, 2017·4 cites·18 claims
- 1488US6334176B1Method and apparatus for generating an alignment control vectorMOTOROLA INC·Filed 1998·Granted Dec 25, 2001·143 cites·13 claims
- 1588US6202130B1Data processing system for processing vector data and method thereforMOTOROLA INC·Filed 1998·Granted Mar 13, 2001·162 cites·29 claims
- 1688US5996057AData processing system and method of permutation with replication within a vector register fileAPPLE·Filed 1998·Granted Nov 30, 1999·169 cites·9 claims
- 1787US8893095B2Methods for generating code for an architecture encoding an extended register specificationGSCHWIND MICHAEL KARL·Filed 2012·Granted Nov 18, 2014·7 cites·12 claims
- 1884US9569127B2Computer instructions for limiting access violation reporting when accessing strings and similar data structuresIBM·Filed 2014·Granted Feb 14, 2017·6 cites·15 claims
- 1982US7849294B2Sharing data in internal and memory representations with dynamic data-driven conversionIBM·Filed 2008·Granted Dec 7, 2010·11 cites·24 claims
- 2082US6343337B1Wide shifting in the vector permute unitIBM·Filed 2000·Granted Jan 29, 2002·32 cites·20 claims
- 2181US10423412B2Instructions to count contiguous register elements having a specific value in a selected locationIBM·Filed 2015·Granted Sep 24, 2019·2 cites·11 claims
- 2280US10387150B2Instructions to count contiguous register elements having a specific value in a selected locationIBM·Filed 2015·Granted Aug 20, 2019·2 cites·20 claims
- 2380US9703721B2Processing page fault exceptions in supervisory software when accessing strings and similar data structures using normal load instructionsIBM·Filed 2014·Granted Jul 11, 2017·4 cites·7 claims
- 2480US5825677ANumerically intensive computer acceleratorIBM·Filed 1996·Granted Oct 20, 1998·96 cites·16 claims
- 2580US5680338AMethod and system for vector processing utilizing selected vector elementsIBM·Filed 1995·Granted Oct 21, 1997·96 cites·10 claims
- 2678US9690509B2Computer instructions for limiting access violation reporting when accessing strings and similar data structuresIBM·Filed 2015·Granted Jun 27, 2017·2 cites·10 claims
- 2778US7934081B2Apparatus and method for using branch prediction heuristics for determination of trace formation readinessIBM·Filed 2006·Granted Apr 26, 2011·8 cites·6 claims
- 2878US7836287B2Reducing the fetch time of target instructions of a predicted taken branch instructionIBM·Filed 2008·Granted Nov 16, 2010·7 cites·2 claims
- 2977US7644233B2Apparatus and method for supporting simultaneous storage of trace and standard cache linesIBM·Filed 2006·Granted Jan 5, 2010·8 cites·6 claims
- 3076US10346180B2Simultaneously capturing status information for multiple operating modesIBM·Filed 2017·Granted Jul 9, 2019·1 cites·20 claims
- 3174US10102007B2Simultaneously capturing status information for multiple operating modesIBM·Filed 2016·Granted Oct 16, 2018·1 cites·20 claims
- 3274US8312424B2Methods for generating code for an architecture encoding an extended register specificationGSCHWIND MICHAEL KARL·Filed 2008·Granted Nov 13, 2012·4 cites·11 claims
- 3373US7996618B2Apparatus and method for using branch prediction heuristics for determination of trace formation readinessIBM·Filed 2011·Granted Aug 9, 2011·3 cites·12 claims
- 3472US5890222AMethod and system for addressing registers in a data processing unit in an indirect addressing modeIBM·Filed 1995·Granted Mar 30, 1999·66 cites·3 claims
- 3571US6282628B1Method and system for a result code for a single-instruction multiple-data predicate compare operationIBM·Filed 1999·Granted Aug 28, 2001·57 cites·20 claims
- 3668US11755320B2Compute array of a processor with mixed-precision numerical linear algebra supportIBM·Filed 2021·Granted Sep 12, 2023·0 cites·20 claims
- 3768US8893079B2Methods for generating code for an architecture encoding an extended register specificationGSCHWIND MICHAEL KARL·Filed 2012·Granted Nov 18, 2014·1 cites·9 claims
- 3868US8386712B2Structure for supporting simultaneous storage of trace and standard cache linesIBM·Filed 2008·Granted Feb 26, 2013·4 cites·8 claims
- 3967US7437543B2Reducing the fetch time of target instructions of a predicted taken branch instructionIBM·Filed 2005·Granted Oct 14, 2008·3 cites·2 claims
- 4066US11972259B2Instructions to count a number of contiguous register elements having specific values in a selected locationIBM·Filed 2019·Granted Apr 30, 2024·0 cites·17 claims
- 4166US11972260B2Instructions to count a number of contiguous register elements having specific values in a selected locationIBM·Filed 2019·Granted Apr 30, 2024·0 cites·9 claims
- 4265US11036519B2Simultaneously capturing status information for multiple operating modesIBM·Filed 2019·Granted Jun 15, 2021·0 cites·20 claims
- 4365US10540512B2Exception preserving parallel data processing of string and unstructured textIBM·Filed 2015·Granted Jan 21, 2020·1 cites·3 claims
- 4465US6202141B1Method and apparatus for performing vector operation using separate multiplication on odd and even data elements of source vectorsIBM·Filed 1998·Granted Mar 13, 2001·46 cites·48 claims
- 4564US9727336B2Fine-grained instruction enablement at sub-function granularity based on an indicated subrange of registersGSCHWIND MICHAEL K·Filed 2011·Granted Aug 8, 2017·1 cites·16 claims
- 4664US9411585B2Multi-addressable register files and format conversions associated therewithGSCHWIND MICHAEL K·Filed 2011·Granted Aug 9, 2016·1 cites·16 claims
- 4763US11188328B2Compute array of a processor with mixed-precision numerical linear algebra supportIBM·Filed 2019·Granted Nov 30, 2021·0 cites·20 claims
- 4862US7610449B2Apparatus and method for saving power in a trace cacheIBM·Filed 2006·Granted Oct 27, 2009·2 cites·12 claims
- 4957US10152324B2Virtualization in a bi-endian-mode processor architectureIBM·Filed 2014·Granted Dec 11, 2018·0 cites·16 claims
- 5056US10120682B2Virtualization in a bi-endian-mode processor architectureIBM·Filed 2014·Granted Nov 6, 2018·0 cites·11 claims
Showing the top 50 of 79 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →