Inventor · disambiguated record
Bruce Joseph Ronchetti
Also filed as: RONCHETTI BRUCE J · RONCHETTI BRUCE JOSEPH
29 granted patents·570 citations·filing 1998–2018
97Inventor score
Technology areasG06F
Top patents by PatentIndex Score
29 records- 0196US9672043B2Processing of multiple instruction streams in a parallel slice processorIBM·Filed 2014·Granted Jun 6, 2017·29 cites·8 claims
- 0295US9690586B2Processing of multiple instruction streams in a parallel slice processorIBM·Filed 2014·Granted Jun 27, 2017·26 cites·4 claims
- 0395US9665372B2Parallel slice processor with dynamic instruction stream mappingIBM·Filed 2014·Granted May 30, 2017·25 cites·16 claims
- 0494US9690585B2Parallel slice processor with dynamic instruction stream mappingIBM·Filed 2014·Granted Jun 27, 2017·22 cites·9 claims
- 0592US9977678B2Reconfigurable parallel execution and load-store slice processorIBM·Filed 2015·Granted May 22, 2018·7 cites·10 claims
- 0690US9971602B2Reconfigurable processing method with modes controlling the partitioning of clusters and cache slicesIBM·Filed 2015·Granted May 15, 2018·6 cites·5 claims
- 0786US10083039B2Reconfigurable processor with load-store slices supporting reorder and controlling access to cache slicesIBM·Filed 2018·Granted Sep 25, 2018·3 cites·20 claims
- 0886US7350051B2Method to optimize effective page number to real page number translation path from page table entries match resumption of execution streamIBM·Filed 2005·Granted Mar 25, 2008·15 cites·6 claims
- 0986US7318127B2Method, apparatus, and computer program product for sharing data in a cache among threads in an SMT processorIBM·Filed 2005·Granted Jan 8, 2008·17 cites·14 claims
- 1084US8271765B2Managing instructions for more efficient load/store unit usageBOSE PRADIP·Filed 2009·Granted Sep 18, 2012·13 cites·13 claims
- 1184US7284094B2Mechanism and apparatus allowing an N-way set associative cache, implementing a hybrid pseudo-LRU replacement algorithm, to have N L1 miss fetch requests simultaneously inflight regardless of their congruence classIBM·Filed 2005·Granted Oct 16, 2007·14 cites·18 claims
- 1282US10983800B2Reconfigurable processor with load-store slices supporting reorder and controlling access to cache slicesIBM·Filed 2018·Granted Apr 20, 2021·2 cites·20 claims
- 1381US10157064B2Processing of multiple instruction streams in a parallel slice processorIBM·Filed 2017·Granted Dec 18, 2018·2 cites·15 claims
- 1481US8156287B2Adaptive data prefetchBOSE PRADIP·Filed 2009·Granted Apr 10, 2012·11 cites·16 claims
- 1578US6237081B1Queuing method and apparatus for facilitating the rejection of sequential instructions in a processorIBM·Filed 1998·Granted May 22, 2001·81 cites·20 claims
- 1677US7571283B2Mechanism in a multi-threaded microprocessor to maintain best case demand instruction redispatchIBM·Filed 2008·Granted Aug 4, 2009·7 cites·11 claims
- 1775US6640293B1Apparatus and method of utilizing Alias Hit signals to detect errors within the real address tag arraysIBM·Filed 2000·Granted Oct 28, 2003·21 cites·15 claims
- 1873US8086801B2Loading data to vector renamed register from across multiple cache linesHRUSECKY DAVID A·Filed 2009·Granted Dec 27, 2011·8 cites·20 claims
- 1973US6266768B1System and method for permitting out-of-order execution of load instructionsIBM·Filed 1998·Granted Jul 24, 2001·63 cites·16 claims
- 2072US7380062B2Mechanism in a multi-threaded microprocessor to maintain best case demand instruction redispatchIBM·Filed 2005·Granted May 27, 2008·5 cites·9 claims
- 2170US6349382B1System for store forwarding assigning load and store instructions to groups and reorder queues to keep track of program orderIBM·Filed 1999·Granted Feb 19, 2002·56 cites·9 claims
- 2266US6336168B1System and method for merging multiple outstanding load miss instructionsIBM·Filed 1999·Granted Jan 1, 2002·46 cites·19 claims
- 2359US7660965B2Method to optimize effective page number to real page number translation path from page table entries match resumption of execution streamIBM·Filed 2008·Granted Feb 9, 2010·1 cites·12 claims
- 2457US7752354B2Auxiliary mechanism to manage instruction restart and restart coming in a lookahead processorIBM·Filed 2005·Granted Jul 6, 2010·1 cites·19 claims
- 2557US6981128B2Atomic quad word storage in a simultaneous multithreaded systemIBM·Filed 2003·Granted Dec 27, 2005·5 cites·9 claims
- 2657US6484230B1Method and system for speculatively processing a load instruction before completion of a preceding synchronization instructionIBM·Filed 1998·Granted Nov 19, 2002·32 cites·20 claims
- 2756US6301654B1System and method for permitting out-of-order execution of load and store instructionsIBM·Filed 1998·Granted Oct 9, 2001·34 cites·21 claims
- 2842US6178497B1System and method for determining the relative age of instructions in a processorIBM·Filed 1998·Granted Jan 23, 2001·14 cites·13 claims
- 2932US6490653B1Method and system for optimally issuing dependent instructions based on speculative L2 cache hit in a data processing systemIBM·Filed 1999·Granted Dec 3, 2002·4 cites·15 claims
Join the waitlist — get patent alerts
Get an alert when Bruce Joseph Ronchetti files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →