Inventor · disambiguated record
Bryan L. Spry
Also filed as: SPRY BRYAN · SPRY BRYAN L
14 granted patents·3 pending applications·129 citations·filing 2005–2017
92Inventor score
Top patents by PatentIndex Score
17 records- 0192US7886174B2Memory link trainingINTEL CORP·Filed 2007·Granted Feb 8, 2011·31 cites·11 claims
- 0289US9330734B2Method and apparatus for dynamically adjusting voltage reference to optimize an I/O systemINTEL CORP·Filed 2013·Granted May 3, 2016·9 cites·13 claims
- 0387US8819474B2Active training of memory command timingSCHOENBORN THEODORE Z·Filed 2009·Granted Aug 26, 2014·21 cites·22 claims
- 0486US8582374B2Method and apparatus for dynamically adjusting voltage reference to optimize an I/O systemMOZAK CHRISTOPHER·Filed 2009·Granted Nov 12, 2013·18 cites·19 claims
- 0584US10347319B2Method and apparatus for dynamically adjusting voltage reference to optimize an I/O systemINTEL CORP·Filed 2016·Granted Jul 9, 2019·5 cites·19 claims
- 0683US8331176B2Method and system for evaluating effects of signal phase difference on a memory systemMOZAK CHRISTOPHER P·Filed 2009·Granted Dec 11, 2012·16 cites·19 claims
- 0779US9373365B2Method and apparatus for dynamically adjusting voltage reference to optimize an I/O systemINTEL CORP·Filed 2014·Granted Jun 21, 2016·4 cites·17 claims
- 0878US7590805B2Monitor implementation in a multicore processor with inclusive LLCINTEL CORP·Filed 2005·Granted Sep 15, 2009·9 cites·12 claims
- 0974US9910814B2Method, apparatus and system for single-ended communication of transaction layer packetsINTEL CORP·Filed 2015·Granted Mar 6, 2018·2 cites·17 claims
- 1072US8868992B2Robust memory link testing using memory controllerSPRY BRYAN L·Filed 2009·Granted Oct 21, 2014·10 cites·13 claims
- 1162US7779188B2System and method to reduce memory latency in microprocessor systems connected with a busINTEL CORP·Filed 2005·Granted Aug 17, 2010·3 cites·24 claims
- 1260US9734116B2Method, apparatus and system for configuring a protocol stack of an integrated circuit chipSPRY BRYAN L·Filed 2015·Granted Aug 15, 2017·1 cites·20 claims
- 1353US10496152B2Power control techniques for integrated PCIe controllersINTEL CORP·Filed 2013·Granted Dec 3, 2019·0 cites·25 claims
- 1448US10282341B2Method, apparatus and system for configuring a protocol stack of an integrated circuit chipINTEL CORP·Filed 2017·Granted May 7, 2019·0 cites·15 claims
- 1540US2007005865A1Enforcing global ordering using an inter-queue ordering mechanismSPRY BRYAN L·Filed 2005·Application pending·0 cites
- 1638US2008162799A1Mechanism for write optimization to a memory deviceSPRY BRYAN·Filed 2006·Application pending·0 cites
- 1733US2017346596A1Method, apparatus, and system for signal equalizationINTEL CORP·Filed 2016·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →