Inventor · disambiguated record
Brian Michael Stempel
Also filed as: STEMPEL BRIAN · STEMPEL BRIAN M · STEMPEL BRIAN MICHAEL
47 granted patents·13 pending applications·255 citations·filing 2004–2019
98Inventor score
Technology areasG06F
Top patents by PatentIndex Score
60 records- 0196US7716460B2Effective use of a BHT in processor having variable length instruction set execution modesQUALCOMM INC·Filed 2006·Granted May 11, 2010·51 cites·16 claims
- 0290US8438372B2Link stack repair of erroneous speculative updateDIEFFENDERFER JAMES NORRIS·Filed 2011·Granted May 7, 2013·15 cites·27 claims
- 0387US7278012B2Method and apparatus for efficiently accessing first and second branch history tables to predict branch instructionsQUALCOMM INC·Filed 2005·Granted Oct 2, 2007·18 cites·22 claims
- 0485US7676659B2System, method and software to preload instructions from a variable-length instruction set with proper pre-decodingQUALCOMM INC·Filed 2007·Granted Mar 9, 2010·14 cites·24 claims
- 0583US7971044B2Link stack repair of erroneous speculative updateQUALCOMM INC·Filed 2007·Granted Jun 28, 2011·11 cites·23 claims
- 0682US9477478B2Multi level indirect predictor using confidence counter and program counter address filter schemeKOTHARI KULIN N·Filed 2012·Granted Oct 25, 2016·10 cites·17 claims
- 0782US7711927B2System, method and software to preload instructions from an instruction set other than one currently executingQUALCOMM INC·Filed 2007·Granted May 4, 2010·10 cites·19 claims
- 0879US7805588B2Caching memory attribute indicators with cached memory data fieldQUALCOMM INC·Filed 2005·Granted Sep 28, 2010·9 cites·26 claims
- 0979US7421568B2Power saving methods and apparatus to selectively enable cache bits based on known processor stateQUALCOMM INC·Filed 2005·Granted Sep 2, 2008·9 cites·18 claims
- 1078US11550723B2Method, apparatus, and system for memory bandwidth aware data prefetchingQUALCOMM INC·Filed 2018·Granted Jan 10, 2023·2 cites·26 claims
- 1176US9329930B2Cache memory error detection circuits for detecting bit flips in valid indicators in cache memory following invalidate operations, and related methods and processor-based systemsQUALCOMM INC·Filed 2014·Granted May 3, 2016·4 cites·28 claims
- 1274US7478228B2Apparatus for generating return address predictions for implicit and explicit subroutine callsQUALCOMM INC·Filed 2006·Granted Jan 13, 2009·5 cites·13 claims
- 1374US7415638B2Pre-decode error handling via branch correctionQUALCOMM INC·Filed 2004·Granted Aug 19, 2008·17 cites·22 claims
- 1473US7984279B2System and method for using a working global history registerQUALCOMM INC·Filed 2006·Granted Jul 19, 2011·6 cites·18 claims
- 1573US7827392B2Sliding-window, block-based branch target address cacheQUALCOMM INC·Filed 2006·Granted Nov 2, 2010·6 cites·16 claims
- 1673US7769983B2Caching instructions for a multiple-state processorQUALCOMM INC·Filed 2005·Granted Aug 3, 2010·6 cites·23 claims
- 1772US8943300B2Method and apparatus for generating return address predictions for implicit and explicit subroutine calls using predecode informationSTEMPEL BRIAN MICHAEL·Filed 2008·Granted Jan 27, 2015·5 cites·17 claims
- 1871US7404042B2Handling cache miss in an instruction crossing a cache line boundaryQUALCOMM INC·Filed 2005·Granted Jul 22, 2008·5 cites·18 claims
- 1970US10956162B2Operand-based reach explicit dataflow processors, and related methods and computer-readable mediaMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2019·Granted Mar 23, 2021·1 cites·30 claims
- 2070US9477476B2Fusing immediate value, write-based instructions in instruction processing circuits, and related processor systems, methods, and computer-readable mediaQUALCOMM INC·Filed 2012·Granted Oct 25, 2016·3 cites·25 claims
- 2169US7962725B2Pre-decoding variable length instructionsQUALCOMM INC·Filed 2006·Granted Jun 14, 2011·4 cites·18 claims
- 2268US8145883B2Preloading instructions from an instruction set other than a currently executing instruction setSARTORIUS THOMAS ANDREW·Filed 2010·Granted Mar 27, 2012·2 cites·27 claims
- 2368US7281120B2Apparatus and method for decreasing the latency between an instruction cache and a pipeline processorIBM·Filed 2004·Granted Oct 9, 2007·11 cites·3 claims
- 2466US7650466B2Method and apparatus for managing cache partitioning using a dynamic boundaryQUALCOMM INC·Filed 2005·Granted Jan 19, 2010·3 cites·24 claims
- 2565US8352713B2Debug circuit comparing processor instruction set operating modeQUALCOMM INC·Filed 2006·Granted Jan 8, 2013·4 cites·35 claims
- 2665US8082428B2Methods and system for resolving simultaneous predicted branch instructionsSMITH RODNEY WAYNE·Filed 2009·Granted Dec 20, 2011·3 cites·14 claims
- 2762US7917731B2Method and apparatus for prefetching non-sequential instruction addressesQUALCOMM INC·Filed 2006·Granted Mar 29, 2011·2 cites·26 claims
- 2861US7406613B2Translation lookaside buffer (TLB) suppression for intra-page program counter relative or absolute address branch instructionsQUALCOMM INC·Filed 2004·Granted Jul 29, 2008·7 cites·22 claims
- 2960US9460018B2Method and apparatus for tracking extra data permissions in an instruction cacheDEBRUYNE LESLIE MARK·Filed 2012·Granted Oct 4, 2016·2 cites·26 claims
- 3060US9411590B2Method to improve speed of executing return branch instructions in a processorQUALCOMM INC·Filed 2013·Granted Aug 9, 2016·1 cites·5 claims
- 3160US9195466B2Fusing conditional write instructions having opposite conditions in instruction processing circuits, and related processor systems, methods, and computer-readable mediaQUALCOMM INC·Filed 2012·Granted Nov 24, 2015·1 cites·25 claims
- 3260US8898437B2Predecode repair cache for instructions that cross an instruction cache lineSMITH RODNEY WAYNE·Filed 2007·Granted Nov 25, 2014·3 cites·21 claims
- 3360US7617387B2Methods and system for resolving simultaneous predicted branch instructionsQUALCOMM INC·Filed 2006·Granted Nov 10, 2009·1 cites·16 claims
- 3459US8291202B2Apparatus and methods for speculative interrupt vector prefetchingSTREETT DAREN EUGENE·Filed 2008·Granted Oct 16, 2012·3 cites·25 claims
- 3559US7711930B2Apparatus and method for decreasing the latency between instruction cache and a pipeline processorIBM·Filed 2007·Granted May 4, 2010·1 cites·12 claims
- 3653US10108419B2Dependency-prediction of instructionsQUALCOMM INC·Filed 2014·Granted Oct 23, 2018·0 cites·30 claims
- 3753US8185725B2Selective powering of a BHT in a processor having variable length instructionsSTEMPEL BRIAN MICHAEL·Filed 2009·Granted May 22, 2012·0 cites·60 claims
- 3851US11061822B2Method, apparatus, and system for reducing pipeline stalls due to address translation missesQUALCOMM INC·Filed 2018·Granted Jul 13, 2021·0 cites·24 claims
- 3950US8438371B2Link stack repair of erroneous speculative updateDIEFFENDERFER JAMES NORRIS·Filed 2011·Granted May 7, 2013·0 cites·24 claims
- 4049US10877895B2Method, apparatus, and system for prefetching exclusive cache coherence state for store instructionsQUALCOMM INC·Filed 2018·Granted Dec 29, 2020·0 cites·23 claims
- 4149US9823929B2Optimizing performance for context-dependent instructionsQUALCOMM INC·Filed 2013·Granted Nov 21, 2017·0 cites·32 claims
- 4249US9317293B2Establishing a branch target instruction cache (BTIC) entry for subroutine returns to reduce execution pipeline bubbles, and related systems, methods, and computer-readable mediaQUALCOMM INC·Filed 2013·Granted Apr 19, 2016·0 cites·28 claims
- 4349US9146741B2Eliminating redundant masking operations instruction processing circuits, and related processor systems, methods, and computer-readable mediaQUALCOMM INC·Filed 2012·Granted Sep 29, 2015·0 cites·20 claims
- 4448US10318436B2Precise invalidation of virtually tagged cachesQUALCOMM INC·Filed 2017·Granted Jun 11, 2019·0 cites·30 claims
- 4548US9858077B2Issuing instructions to execution pipelines based on register-associated preferences, and related instruction processing circuits, processor systems, methods, and computer-readable mediaQUALCOMM INC·Filed 2013·Granted Jan 2, 2018·0 cites·22 claims
- 4647US8819342B2Methods and apparatus for managing page crossing instructions with different cacheabilityQUALCOMM INC·Filed 2012·Granted Aug 26, 2014·0 cites·21 claims
- 4746US2011047357A1Methods and Apparatus to Predict Non-Execution of Conditional Non-branching InstructionsQUALCOMM INC·Filed 2009·Application pending·0 cites
- 4844US2006048011A1Performance profiling of microprocessor systems using debug hardware and performance monitorIBM·Filed 2004·Application pending·0 cites
- 4943US2013326195A1Preventing execution of parity-error-induced unpredictable instructions, and related processor systems, methods, and computer-readable mediaQUALCOMM INC·Filed 2013·Application pending·0 cites
- 5043US2014281429A1Eliminating redundant synchronization barriers in instruction processing circuits, and related processor systems, methods, and computer-readable mediaQUALCOMM INC·Filed 2013·Application pending·0 cites
Showing the top 50 of 60 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →