Inventor · disambiguated record
Bruce Ernest Whittaker
Also filed as: WHITTAKER BRUCE E · WHITTAKER BRUCE ERNEST
50 granted patents·1,326 citations·filing 1984–2003
99Inventor score
Top patents by PatentIndex Score
50 records- 0195US4677566APower control network for multiple digital modulesBURROUGHS CORP·Filed 1984·Granted Jun 30, 1987·163 cites·5 claims
- 0288US5832250AMulti set cache structure having parity RAMs holding parity bits for tag data and for status data utilizing prediction circuitry that predicts and generates the needed parity bitsUNISYS CORP·Filed 1996·Granted Nov 3, 1998·147 cites·7 claims
- 0386US4635195APower control network using reliable communications protocolBURROUGHS CORP·Filed 1984·Granted Jan 6, 1987·74 cites·5 claims
- 0484US7171593B1Displaying abnormal and error conditions in system state analysisUNISYS CORP·Filed 2003·Granted Jan 30, 2007·52 cites·32 claims
- 0581US5706297ASystem for adapting maintenance operations to JTAG and non-JTAG modulesUNISYS CORP·Filed 1995·Granted Jan 6, 1998·51 cites·4 claims
- 0672US5598551ACache invalidation sequence system utilizing odd and even invalidation queues with shorter invalidation cyclesUNISYS CORP·Filed 1996·Granted Jan 28, 1997·72 cites·5 claims
- 0772US5506967AStorage queue with adjustable level thresholds for cache invalidation systems in cache oriented computer architecturesUNISYS CORP·Filed 1993·Granted Apr 9, 1996·59 cites·10 claims
- 0872US5355468ASystem for halting synchronous digital modulesUNISYS CORP·Filed 1992·Granted Oct 11, 1994·58 cites·7 claims
- 0970US5086427AClocked logic circuitry preventing double driving on shared data busUNISYS CORP·Filed 1990·Granted Feb 4, 1992·36 cites·2 claims
- 1067US5729712ASmart fill system for multiple cache networkUNISYS CORP·Filed 1996·Granted Mar 17, 1998·51 cites·7 claims
- 1166US5790813APre-arbitration system allowing look-around and bypass for significant operationsUNISYS CORP·Filed 1996·Granted Aug 4, 1998·48 cites·4 claims
- 1265US7401261B1Automatic analysis of memory operations using panel dump fileUNISYS CORP·Filed 2003·Granted Jul 15, 2008·10 cites·30 claims
- 1360US5146596AMultiprocessor multifunction arbitration system with two levels of bus access including priority and normal requestsUNISYS CORP·Filed 1990·Granted Sep 8, 1992·37 cites·3 claims
- 1459US6295563B1Control system for recreating of data output clock frequency which matches data input clock frequency during data transferringUNISYS CORP·Filed 1998·Granted Sep 25, 2001·21 cites·8 claims
- 1559US5889959AFast write initialization method and system for loading channel adapter microcodeUNISYS CORP·Filed 1996·Granted Mar 30, 1999·37 cites·4 claims
- 1659US5561773AProgrammable, multi-purpose virtual pin multiplierUNISYS CORP·Filed 1993·Granted Oct 1, 1996·14 cites·6 claims
- 1755US5822334AHigh speed initialization system for RAM devices using JTAG loop for providing valid parity bitsUNISYS CORP·Filed 1996·Granted Oct 13, 1998·15 cites·7 claims
- 1855US5666513AAutomatic reconfiguration of multiple-way cache system allowing uninterrupted continuing processor operationUNISYS CORP·Filed 1996·Granted Sep 9, 1997·30 cites·3 claims
- 1954US5717872AFlexible, soft, random-like counter system for bus protocol waiting periodsUNISYS CORP·Filed 1996·Granted Feb 10, 1998·27 cites·5 claims
- 2052US5687348AVariable-depth, self-regulating cache queue flushing systemUNISYS CORP·Filed 1996·Granted Nov 11, 1997·25 cites·6 claims
- 2152US5459836AInter-processor communication netUNISYS CORP·Filed 1992·Granted Oct 17, 1995·25 cites·10 claims
- 2252US5117428ASystem for memory data integrityUNISYS CORP·Filed 1989·Granted May 26, 1992·18 cites·16 claims
- 2351US7793229B1Recording relevant information in a GUI window of a panel dump browser toolUNISYS CORP·Filed 2003·Granted Sep 7, 2010·2 cites·8 claims
- 2449US5087953AFlexible gate array system for combinatorial logicUNISYS CORP·Filed 1990·Granted Feb 11, 1992·9 cites·8 claims
- 2547US5640531AEnhanced computer operational system using auxiliary mini-cache for enhancement to general cacheUNISYS CORP·Filed 1996·Granted Jun 17, 1997·21 cites·10 claims
- 2645US6070166AApparatus and method for compressing a plurality of contiguous addresses to form a compressed block address using the first address of the contiguous addresses and a block identifier bitUNISYS CORP·Filed 1997·Granted May 30, 2000·12 cites·10 claims
- 2745US5699552ASystem for improved processor throughput with enhanced cache utilization using specialized interleaving operationsUNISYS CORP·Filed 1996·Granted Dec 16, 1997·18 cites·10 claims
- 2844US6070233AProcessor bus traffic optimization system for multi-level cache utilizing reflection status bit to indicate data inclusion in higher level cacheUNISYS CORP·Filed 1997·Granted May 30, 2000·16 cites·2 claims
- 2944US5737567AFast write initialization system for microcode RAM via data path array using pre-loaded flash memory an programmable control logic arrayUNISYS CORP·Filed 1995·Granted Apr 7, 1998·17 cites·6 claims
- 3044US5321814ASystem for optional module detection and reconfigurationUNISYS CORP·Filed 1992·Granted Jun 14, 1994·16 cites·3 claims
- 3144US5117132AFlexible utilization of general flip-flops in programmable array logicUNISYS CORP·Filed 1991·Granted May 26, 1992·7 cites·13 claims
- 3242US5850513AProcessor path emulation system providing fast readout and verification of main memory by maintenance controller interface to maintenance subsystemUNISYS CORP·Filed 1996·Granted Dec 15, 1998·10 cites·6 claims
- 3342US5052001AMultiple memory bank parity checking systemUNISYS CORP·Filed 1989·Granted Sep 24, 1991·10 cites·19 claims
- 3442US4658353ASystem control network for multiple processor modulesBURROUGHS CORP·Filed 1984·Granted Apr 14, 1987·11 cites·12 claims
- 3541US6000015AProcessor bus traffic optimization system for multi-level cache utilizing reflection status bit to indicate data inclusion in a higher level cacheUNISYS CORP·Filed 1999·Granted Dec 7, 1999·13 cites·7 claims
- 3641US5537609AMini cache operational module for enhancement to general cacheUNISYS CORP·Filed 1995·Granted Jul 16, 1996·14 cites·8 claims
- 3739US5717900AAdjusting priority cache access operations with multiple level priority states between a central processor and an invalidation queueUNISYS CORP·Filed 1996·Granted Feb 10, 1998·10 cites·10 claims
- 3839US5689680ACache memory system and method for accessing a coincident cache with a bit-sliced architectureUNISYS CORP·Filed 1993·Granted Nov 18, 1997·9 cites·3 claims
- 3938US5088092AWidth-expansible memory integrity structureUNISYS CORP·Filed 1989·Granted Feb 11, 1992·8 cites·2 claims
- 4037US5418935AApparatus for preventing double drive occurrences on a common bus by delaying enablement of one driver after indication of disablement to other driver is receivedUNISYS CORP·Filed 1993·Granted May 23, 1995·9 cites·4 claims
- 4136US6041337ALinear function generator method with counter for implementation of control signals in digital logicUNISYS CORP·Filed 1997·Granted Mar 21, 2000·8 cites·10 claims
- 4236US5935200AExponential functional relationship generator method and system for implementation in digital logicUNISYS CORP·Filed 1997·Granted Aug 10, 1999·8 cites·8 claims
- 4335US5706424ASystem for fast read and verification of microcode RAMUNISYS CORP·Filed 1995·Granted Jan 6, 1998·7 cites·6 claims
- 4435US5087839AMethod of providing flexibility and alterability in VLSI gate array chipsUNISYS CORP·Filed 1990·Granted Feb 11, 1992·6 cites·11 claims
- 4534US5768299ADerived generation system for parity bits with bi-directional, crossed-fields utilizing stored flip-bit featureUNISYS CORP·Filed 1996·Granted Jun 16, 1998·6 cites·5 claims
- 4634US5701431AMethod and system for randomly selecting a cache set for cache fill operationsUNISYS CORP·Filed 1996·Granted Dec 23, 1997·6 cites·4 claims
- 4731US5928310ADigital device control method and system via linear function generator implementation using adder for interceptUNISYS CORP·Filed 1997·Granted Jul 27, 1999·2 cites·8 claims
- 4830US5642486AInvalidation queue with "bit-sliceability"UNISYS CORP·Filed 1993·Granted Jun 24, 1997·1 cites·2 claims
- 4930US5530727AHalf synchronizer circuit interface systemUNISYS CORP·Filed 1994·Granted Jun 25, 1996·0 cites·7 claims
- 5027US5991853AMethods for accessing coincident cache with a bit-sliced architectureUNISYS CORP·Filed 1997·Granted Nov 23, 1999·0 cites·3 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →