Inventor · disambiguated record
Bruce E. Zahn
Also filed as: ZAHN BRUCE · ZAHN BRUCE E
6 granted patents·4 pending applications·11 citations·filing 2008–2014
75Inventor score
Top patents by PatentIndex Score
10 records- 0168US8461893B2Uniform-footprint programmable multi-stage delay cellGASPER MARTIN J·Filed 2011·Granted Jun 11, 2013·4 cites·28 claims
- 0266US8694937B2Implementing and checking electronic circuits with flexible ramptime limits and tools for performing the sameLSI CORP·Filed 2012·Granted Apr 8, 2014·2 cites·14 claims
- 0360US8713506B2System and method for employing signoff-quality timing analysis information concurrently in multiple scenarios to reduce dynamic power in an electronic circuit and an apparatus incorporating the sameZAHN BRUCE·Filed 2011·Granted Apr 29, 2014·2 cites·20 claims
- 0454US8776003B2System and method for employing side transition times from signoff-quality timing analysis information to reduce leakage power in an electronic circuit and an electronic design automation tool incorporating the sameZAHN BRUCE E·Filed 2012·Granted Jul 8, 2014·2 cites·22 claims
- 0552US8271922B2System and method for clock optimization to achieve timing signoff in an electronic circuit and electronic design automation tool incorporating the sameZAHN BRUCE E·Filed 2009·Granted Sep 18, 2012·1 cites·20 claims
- 0645US8332792B2Implementing and checking electronic circuits with flexible ramptime limits and tools for performing the sameTETELBAUM ALEXANDER·Filed 2010·Granted Dec 11, 2012·0 cites·16 claims
- 0744US2010153897A1System and method for employing signoff-quality timing analysis information concurrently in multiple scenarios to reduce leakage power in an electronic circuit and electronic design automation tool incorporating the sameLSI CORP·Filed 2008·Application pending·0 cites
- 0843US2010050144A1System and method for employing signoff-quality timing analysis information to reduce leakage power in an electronic circuit and electronic design automation tool incorporating the sameLSI CORP·Filed 2008·Application pending·0 cites
- 0941US2014059505A1Method for designing integrated circuits employing correct-by-construction progressive modeling and an apparatus employing the methodBLAIR GERARD M·Filed 2012·Application pending·0 cites
- 1040US2015269304A1System and method for employing signoff-quality timing analysis information concurrently in multiple scenarios to reduce total power within a circuit designLSI CORP·Filed 2014·Application pending·0 cites
Join the waitlist — get patent alerts
Get an alert when Bruce E. Zahn files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →