Inventor · disambiguated record
Bupesh Pandita
Also filed as: PANDITA BUPESH
20 granted patents·2 pending applications·128 citations·filing 2014–2025
93Inventor score
Top patents by PatentIndex Score
22 records- 0198US9778672B1Gate boosted low drop regulatorQUALCOMM INC·Filed 2016·Granted Oct 3, 2017·44 cites·16 claims
- 0296US11658696B2Network transceiver with VGA channel specific equalizationMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2021·Granted May 23, 2023·5 cites·17 claims
- 0395US9602317B1Apparatus and method for combining currents from passive equalizer in sense amplifierQUALCOMM INC·Filed 2015·Granted Mar 21, 2017·20 cites·18 claims
- 0493US10355702B2Hybrid phase-locked loopQUALCOMM INC·Filed 2017·Granted Jul 16, 2019·12 cites·18 claims
- 0593US9971312B1Pulse to digital converterQUALCOMM INC·Filed 2017·Granted May 15, 2018·10 cites·30 claims
- 0686US9577646B1Fractional phase locked loop (PLL) architectureQUALCOMM INC·Filed 2015·Granted Feb 21, 2017·7 cites·24 claims
- 0785US11722140B2Phase-locked-loop circuit employing a hybrid loop filter with sample and hold capacitors for reduced signal jitter, and related methodsMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2021·Granted Aug 8, 2023·2 cites·21 claims
- 0881US12212327B2Phase-locked loops (PLL), including time-to-digital converter (TDC) gain calibration circuits and related methodsMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2023·Granted Jan 28, 2025·1 cites·23 claims
- 0981US10476434B1Quadrature clock generation with injection lockingQUALCOMM INC·Filed 2018·Granted Nov 12, 2019·4 cites·30 claims
- 1081US9998126B1Delay locked loop (DLL) employing pulse to digital converter (PDC) for calibrationQUALCOMM INC·Filed 2017·Granted Jun 12, 2018·4 cites·30 claims
- 1181US9520872B2Linear equalizer with variable gainQUALCOMM INC·Filed 2014·Granted Dec 13, 2016·5 cites·18 claims
- 1278US9729163B1Apparatus and method for in situ analog signal diagnostic and debugging with calibrated analog-to-digital converterQUALCOMM INC·Filed 2016·Granted Aug 8, 2017·4 cites·30 claims
- 1378US9485085B2Phase locked loop (PLL) architectureQUALCOMM INC·Filed 2015·Granted Nov 1, 2016·5 cites·28 claims
- 1474US2025293904A1Adaptive channel equalization for a duo-binary transceiverMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2025·Application pending·0 cites
- 1571US12355596B2Adaptive channel equalization for a duo-binary transceiverMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2023·Granted Jul 8, 2025·0 cites·22 claims
- 1670US12483288B2Network transceiver with VGA channel specific equalizationMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2023·Granted Nov 25, 2025·0 cites·17 claims
- 1769US10419204B2Serializer-deserializer with frequency doublerQUALCOMM INC·Filed 2018·Granted Sep 17, 2019·1 cites·10 claims
- 1869US10355701B2Apparatus and method for frequency calibration of voltage controlled oscillator (VCO) including determining VCO frequency rangeQUALCOMM INC·Filed 2017·Granted Jul 16, 2019·2 cites·27 claims
- 1965US10965442B2Low-power, low-latency time-to-digital-converter-based serial linkQUALCOMM INC·Filed 2018·Granted Mar 30, 2021·1 cites·17 claims
- 2060US10389366B2SerDes with adaptive clock data recoveryQUALCOMM INC·Filed 2018·Granted Aug 20, 2019·1 cites·18 claims
- 2150US11705890B2Programmable analog calibration circuit supporting iterative measurement of an input signal from a measured circuit, such as for calibration, and related methodsMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2021·Granted Jul 18, 2023·0 cites·34 claims
- 2232US2016216317A1Built-in test structure for a receiverQUALCOMM INC·Filed 2015·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →