Inventor · disambiguated record
Carl S. Dobbs
Also filed as: DOBBS CARL S
39 granted patents·5 pending applications·369 citations·filing 1989–2025
97Inventor score
Top patents by PatentIndex Score
44 records- 0197US9990241B2Processing system with interspersed processors with multi-layer interconnectionCOHERENT LOGIX INC·Filed 2017·Granted Jun 5, 2018·20 cites·20 claims
- 0294US9430369B2Memory-network processor with programmable optimizationsCOHERENT LOGIX INC·Filed 2014·Granted Aug 30, 2016·20 cites·15 claims
- 0394US5173617ADigital phase lock clock generator without local oscillatorMOTOROLA INC·Filed 1989·Granted Dec 22, 1992·81 cites·16 claims
- 0493US8880866B2Method and system for disabling communication paths in a multiprocessor fabric by setting register values to disable the communication paths specified by a configurationDOERR MICHAEL B·Filed 2011·Granted Nov 4, 2014·17 cites·20 claims
- 0592US9612984B2Multiprocessor system with improved secondary interconnection networkCOHERENT LOGIX INC·Filed 2016·Granted Apr 4, 2017·6 cites·20 claims
- 0691US11544072B2Memory-network processor with programmable optimizationsCOHERENT LOGIX INC·Filed 2021·Granted Jan 3, 2023·2 cites·13 claims
- 0791US8963599B2Multi-frequency clock skew control for inter-chip communication in synchronous digital systemsCOHERENT LOGIX INC·Filed 2013·Granted Feb 24, 2015·13 cites·14 claims
- 0889US9292464B2Multiprocessor system with improved secondary interconnection networkCOHERENT LOGIX INC·Filed 2013·Granted Mar 22, 2016·7 cites·30 claims
- 0989US2025117271A1Processing system with interspersed processors dma-fifoHYPERX LOGIC INC·Filed 2024·Application pending·0 cites
- 1088US10838787B2Processing system with interspersed processors with multi-layer interconnectCOHERENT LOGIX INC·Filed 2019·Granted Nov 17, 2020·2 cites·20 claims
- 1188US9720867B2Processing system with interspersed processors with multi-layer interconnectionCOHERENT LOGIX INC·Filed 2016·Granted Aug 1, 2017·3 cites·20 claims
- 1288US9154142B2Multi-frequency clock skew control for inter-chip communication in synchronous digital systemsCOHERENT LOGIX INC·Filed 2015·Granted Oct 6, 2015·6 cites·20 claims
- 1385US2025252065A1Multiprocessor system with improved secondary interconnection networkHYPERX LOGIC INC·Filed 2025·Application pending·0 cites
- 1484US9424213B2Processing system with interspersed processors DMA-FIFOCOHERENT LOGIX INC·Filed 2013·Granted Aug 23, 2016·4 cites·14 claims
- 1583US12306773B2Multiprocessor system with improved secondary interconnection networkCOHERENT LOGIX INC·Filed 2023·Granted May 20, 2025·0 cites·20 claims
- 1681US9450590B2Clock distribution network for multi-frequency multi-processor systemsCOHERENT LOGIX INC·Filed 2013·Granted Sep 20, 2016·4 cites·17 claims
- 1780US5630048ADiagnostic system for run-time monitoring of computer operationsFiled 1994·Granted May 13, 1997·94 cites·10 claims
- 1879US11483580B2Distributed architecture for encoding and delivering video contentCOHERENT LOGIX INC·Filed 2013·Granted Oct 25, 2022·4 cites·59 claims
- 1978US11900124B2Memory-network processor with programmable optimizationsCOHERENT LOGIX INC·Filed 2023·Granted Feb 13, 2024·0 cites·19 claims
- 2077US9430422B2Processing system with interspersed processors with multi-layer interconnectCOHERENT LOGIX INC·Filed 2013·Granted Aug 30, 2016·2 cites·27 claims
- 2175US12197970B2Processing system with interspersed processors DMA-FIFOCOHERENT LOGIX INC·Filed 2021·Granted Jan 14, 2025·0 cites·17 claims
- 2275US10007293B2Clock distribution network for multi-frequency multi-processor systemsCOHERENT LOGIX INC·Filed 2016·Granted Jun 26, 2018·2 cites·15 claims
- 2374US9323714B2Processing system with synchronization instructionCOHERENT LOGIX INC·Filed 2013·Granted Apr 26, 2016·3 cites·27 claims
- 2474US5933594ADiagnostic system for run-time monitoring of computer operationsFiled 1997·Granted Aug 3, 1999·76 cites·20 claims
- 2573US11829320B2Memory network processorCOHERENT LOGIX INC·Filed 2022·Granted Nov 28, 2023·0 cites·16 claims
- 2673US10747709B2Memory network processorCOHERENT LOGIX INC·Filed 2018·Granted Aug 18, 2020·1 cites·17 claims
- 2772US11755504B2Multiprocessor system with improved secondary interconnection networkCOHERENT LOGIX INC·Filed 2020·Granted Sep 12, 2023·0 cites·20 claims
- 2870US10521285B2Processing system with interspersed processors with multi-layer interconnectionCOHERENT LOGIX INC·Filed 2019·Granted Dec 31, 2019·0 cites·20 claims
- 2969US10747689B2Multiprocessor system with improved secondary interconnection networkCOHERENT LOGIX INC·Filed 2019·Granted Aug 18, 2020·0 cites·20 claims
- 3069US9424441B2Multiprocessor fabric having configurable communication that is selectively disabled for secure processingCOHERENT LOGIX INC·Filed 2014·Granted Aug 23, 2016·1 cites·20 claims
- 3168US2020302090A1Selectively Disabling Configurable Communication Paths of a Multiprocessor FabricCOHERENT LOGIX INC·Filed 2020·Application pending·0 cites
- 3267US10185608B2Processing system with interspersed processors with multi-layer interconnectionCOHERENT LOGIX INC·Filed 2018·Granted Jan 22, 2019·0 cites·20 claims
- 3367US9325329B2Automatic selection of on-chip clock in synchronous digital systemsCOHERENT LOGIX INC·Filed 2013·Granted Apr 26, 2016·1 cites·14 claims
- 3466US11016779B2Memory-network processor with programmable optimizationsCOHERENT LOGIX INC·Filed 2019·Granted May 25, 2021·0 cites·20 claims
- 3565US11550750B2Memory network processorCOHERENT LOGIX INC·Filed 2020·Granted Jan 10, 2023·0 cites·15 claims
- 3663US10685143B2Secure boot sequence for selectively disabling configurable communication paths of a multiprocessor fabricCOHERENT LOGIX INC·Filed 2018·Granted Jun 16, 2020·0 cites·18 claims
- 3762US11030023B2Processing system with interspersed processors DMA-FIFOCOHERENT LOGIX INC·Filed 2016·Granted Jun 8, 2021·0 cites·20 claims
- 3862US10185672B2Multiprocessor system with improved secondary interconnection networkCOHERENT LOGIX INC·Filed 2017·Granted Jan 22, 2019·0 cites·20 claims
- 3959US11327753B2Processor instructions to accelerate FEC encoding and decodingCOHERENT LOGIX INC·Filed 2020·Granted May 10, 2022·0 cites·20 claims
- 4058US10007806B2Secure boot sequence for selectively disabling configurable communication paths of a multiprocessor fabricCOHERENT LOGIX INC·Filed 2016·Granted Jun 26, 2018·0 cites·20 claims
- 4158US2024427973A1Modular Design FlowCOHERENT LOGIX INC·Filed 2024·Application pending·0 cites
- 4257US2016328231A1Memory-network processor with programmable optimizationsCOHERENT LOGIX INC·Filed 2016·Application pending·0 cites
- 4351US10691451B2Processor instructions to accelerate FEC encoding and decodingCOHERENT LOGIX INC·Filed 2016·Granted Jun 23, 2020·0 cites·20 claims
- 4451US9558150B2Processing system with synchronization instructionCOHERENT LOGIX INC·Filed 2016·Granted Jan 31, 2017·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →