Inventor · disambiguated record
Cathy May
Also filed as: MAY CATHY
38 granted patents·4 pending applications·513 citations·filing 1998–2019
97Inventor score
Technology areasG06F
Top patents by PatentIndex Score
42 records- 0196US10067713B2Efficient enforcement of barriers with respect to memory move sequencesIBM·Filed 2016·Granted Sep 4, 2018·17 cites·19 claims
- 0296US9785557B1Translation entry invalidation in a multithreaded data processing systemIBM·Filed 2016·Granted Oct 10, 2017·23 cites·20 claims
- 0396US8010763B2Hypervisor-enforced isolation of entities within a single logical partition's virtual address spaceIBM·Filed 2008·Granted Aug 30, 2011·61 cites·21 claims
- 0493US10387686B2Hardware based isolation for secure execution of virtual machinesIBM·Filed 2017·Granted Aug 20, 2019·11 cites·24 claims
- 0593US7904661B2Data stream prefetching in a microprocessorIBM·Filed 2007·Granted Mar 8, 2011·32 cites·13 claims
- 0692US8544022B2Transactional memory preemption mechanismARNDT RICHARD L·Filed 2012·Granted Sep 24, 2013·17 cites·5 claims
- 0791US9772945B1Translation entry invalidation in a multithreaded data processing systemIBM·Filed 2016·Granted Sep 26, 2017·9 cites·20 claims
- 0890US7350029B2Data stream prefetching in a microprocessorIBM·Filed 2005·Granted Mar 25, 2008·22 cites·7 claims
- 0989US8615644B2Processor with hardware thread control logic indicating disable status when instructions accessing shared resources are completed for safe shared resource conditionBRUCE BECKY·Filed 2010·Granted Dec 24, 2013·18 cites·13 claims
- 1089US7389400B2Apparatus and method for selectively invalidating entries in an address translation cacheIBM·Filed 2005·Granted Jun 17, 2008·22 cites·1 claims
- 1188US6202130B1Data processing system for processing vector data and method thereforMOTOROLA INC·Filed 1998·Granted Mar 13, 2001·162 cites·29 claims
- 1285US9430166B2Interaction of transactional storage accesses with other atomic semanticsIBM·Filed 2012·Granted Aug 30, 2016·6 cites·26 claims
- 1385US7949859B2Mechanism for avoiding check stops in speculative accesses while operating in real modeIBM·Filed 2008·Granted May 24, 2011·13 cites·2 claims
- 1484US9047079B2Indicating disabled thread to other threads when contending instructions complete execution to ensure safe shared resource conditionBRUCE BECKY·Filed 2012·Granted Jun 2, 2015·10 cites·7 claims
- 1583US10817434B2Interruptible translation entry invalidation in a multithreaded data processing systemIBM·Filed 2018·Granted Oct 27, 2020·3 cites·16 claims
- 1681US8140759B2Specifying an access hint for prefetching partial cache block data in a cache hierarchyFREY BRADLY GEORGE·Filed 2009·Granted Mar 20, 2012·12 cites·20 claims
- 1780US8424015B2Transactional memory preemption mechanismARNDT RICHARD L·Filed 2010·Granted Apr 16, 2013·5 cites·10 claims
- 1880US7802252B2Method and apparatus for selecting the architecture level to which a processor appears to conformIBM·Filed 2007·Granted Sep 21, 2010·11 cites·20 claims
- 1976US7822942B2Selectively invalidating entries in an address translation cacheIBM·Filed 2008·Granted Oct 26, 2010·7 cites·2 claims
- 2073US11226902B2Translation load instruction with access protectionIBM·Filed 2019·Granted Jan 18, 2022·1 cites·22 claims
- 2172US7370177B2Mechanism for avoiding check stops in speculative accesses while operating in real modeIBM·Filed 2003·Granted May 6, 2008·15 cites·3 claims
- 2270US6823445B2Limiting concurrent modification and execution of instructions to a particular type to avoid unexpected resultsIBM·Filed 2001·Granted Nov 23, 2004·15 cites·19 claims
- 2368US9396115B2Rewind only transactions in a data processing system supporting transactional storage accessesIBM·Filed 2012·Granted Jul 19, 2016·2 cites·21 claims
- 2467US10152322B2Memory move instruction sequence including a stream of copy-type and paste-type instructionsIBM·Filed 2016·Granted Dec 11, 2018·1 cites·18 claims
- 2566US9626187B2Transactional memory system supporting unbroken suspended executionCAIN III HAROLD W·Filed 2010·Granted Apr 18, 2017·2 cites·21 claims
- 2666US9244846B2Ensuring causality of transactional storage accesses interacting with non-transactional storage accessesFREY BRADLY G·Filed 2012·Granted Jan 26, 2016·2 cites·25 claims
- 2766US7143267B2Partitioning prefetch registers to prevent at least in part inconsistent prefetch information from being stored in a prefetch register of a multithreading processorIBM·Filed 2003·Granted Nov 28, 2006·12 cites·8 claims
- 2865US9367264B2Transaction check instruction for memory transactionsIBM·Filed 2013·Granted Jun 14, 2016·1 cites·6 claims
- 2958US10613792B2Efficient enforcement of barriers with respect to memory move sequencesIBM·Filed 2018·Granted Apr 7, 2020·0 cites·19 claims
- 3058US9619345B2Apparatus for determining failure context in hardware transactional memoriesCAIN HAROLD W·Filed 2012·Granted Apr 11, 2017·1 cites·16 claims
- 3154US9367263B2Transaction check instruction for memory transactionsIBM·Filed 2012·Granted Jun 14, 2016·0 cites·15 claims
- 3253US9626256B2Determining failure context in hardware transactional memoriesIBM·Filed 2013·Granted Apr 18, 2017·0 cites·8 claims
- 3351US9268598B2Recording and profiling transaction failure source addresses and states of validity indicator corresponding to addresses of aborted transaction in hardware transactional memoriesBLAINEY ROBERT J·Filed 2012·Granted Feb 23, 2016·0 cites·10 claims
- 3450US9268599B2Recording and profiling transaction failure addresses of the abort-causing and approximate abort-causing data and instructions in hardware transactional memoriesIBM·Filed 2013·Granted Feb 23, 2016·0 cites·5 claims
- 3548US8176254B2Specifying an access hint for prefetching limited use data in a cache hierarchyFREY BRADLY G·Filed 2009·Granted May 8, 2012·0 cites·20 claims
- 3648US2014013055A1Ensuring causality of transactional storage accesses interacting with non-transactional storage accessesFREY BRADLY G·Filed 2013·Application pending·0 cites
- 3747US9342454B2Nested rewind only and non rewind only transactions in a data processing system supporting transactional storage accessesIBM·Filed 2012·Granted May 17, 2016·0 cites·23 claims
- 3847US9081607B2Conditional transaction abort and precise abort handlingIBM·Filed 2012·Granted Jul 14, 2015·0 cites·20 claims
- 3945US2008034193A1System and Method for Providing a Mediated External Exception Extension for a MicroprocessorDAY MICHAEL N·Filed 2006·Application pending·0 cites
- 4045US2005182912A1Method of effective to real address translation for a multi-threaded microprocessorIBM·Filed 2004·Application pending·0 cites
- 4144US2005027960A1Translation look-aside buffer sharing among logical partitionsIBM·Filed 2003·Application pending·0 cites
- 4239US8745307B2Multiple page size segment encodingCHADHA SUNDEEP·Filed 2010·Granted Jun 3, 2014·0 cites·25 claims
Join the waitlist — get patent alerts
Get an alert when Cathy May files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →