Inventor · disambiguated record
Chris Baronne
Also filed as: BARONNE CHRIS
9 granted patents·2 pending applications·1 citations·filing 2020–2025
76Inventor score
Technology areasG06F
Files withMICRON TECHNOLOGY INC11
Top patents by PatentIndex Score
11 records- 0178US11507453B2Low-latency register error correctionMICRON TECHNOLOGY INC·Filed 2020·Granted Nov 22, 2022·1 cites·27 claims
- 0270US11734173B2Memory access bounds checking for a programmable atomic operatorMICRON TECHNOLOGY INC·Filed 2022·Granted Aug 22, 2023·0 cites·24 claims
- 0370US11698791B2On-demand programmable atomic kernel loadingMICRON TECHNOLOGY INC·Filed 2022·Granted Jul 11, 2023·0 cites·26 claims
- 0469US11953989B2Low-latency register error correctionMICRON TECHNOLOGY INC·Filed 2022·Granted Apr 9, 2024·0 cites·17 claims
- 0567US2025224984A1Thread replay to preserve state in a barrel processorMICRON TECHNOLOGY INC·Filed 2025·Application pending·0 cites
- 0664US11409539B2On-demand programmable atomic kernel loadingMICRON TECHNOLOGY INC·Filed 2020·Granted Aug 9, 2022·0 cites·27 claims
- 0764US11379365B2Memory access bounds checking for a programmable atomic operatorMICRON TECHNOLOGY INC·Filed 2020·Granted Jul 5, 2022·0 cites·24 claims
- 0859US12282800B2Thread replay to preserve state in a barrel processorMICRON TECHNOLOGY INC·Filed 2020·Granted Apr 22, 2025·0 cites·25 claims
- 0950US12020064B2Rescheduling a failed memory request in a processorMICRON TECHNOLOGY INC·Filed 2020·Granted Jun 25, 2024·0 cites·24 claims
- 1046US12135987B2Thread scheduling control and memory splitting in a barrel processorMICRON TECHNOLOGY INC·Filed 2020·Granted Nov 5, 2024·0 cites·25 claims
- 1139US2022121483A1Thread execution control in a barrel processorMICRON TECHNOLOGY INC·Filed 2020·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →