Inventor · disambiguated record
Christopher J. Berry
Also filed as: BERRY CHRISTOPHER · BERRY CHRISTOPHER J · BERRY CHRISTOPHER JOSEPH
52 granted patents·5 pending applications·103 citations·filing 1989–2024
97Inventor score
Top patents by PatentIndex Score
57 records- 0183US9910952B2Hierarchically aware interior pinning for large synthesis blocksIBM·Filed 2016·Granted Mar 6, 2018·4 cites·20 claims
- 0282US9703920B2Intra-run design decision process for circuit synthesisIBM·Filed 2015·Granted Jul 11, 2017·3 cites·12 claims
- 0381US9858377B2Constraint-driven pin optimization for hierarchical design convergenceIBM·Filed 2015·Granted Jan 2, 2018·4 cites·19 claims
- 0480US10157255B2Hierarchically aware interior pinning for large synthesis blocksIBM·Filed 2017·Granted Dec 18, 2018·3 cites·18 claims
- 0579US10943051B1Metal fill shape removal from selected netsIBM·Filed 2019·Granted Mar 9, 2021·4 cites·20 claims
- 0679US9734268B2Slack redistribution for additional power recoveryIBM·Filed 2015·Granted Aug 15, 2017·3 cites·11 claims
- 0779US7735051B2Method for replicating and synchronizing a plurality of physical instances with a logical masterIBM·Filed 2006·Granted Jun 8, 2010·10 cites·21 claims
- 0878US9659140B2Critical region identificationIBM·Filed 2015·Granted May 23, 2017·2 cites·6 claims
- 0978US7739538B2Double data rate chaining for synchronous DDR interfacesIBM·Filed 2006·Granted Jun 15, 2010·9 cites·2 claims
- 1076US9934341B2Simulation of modifications to microprocessor designIBM·Filed 2015·Granted Apr 3, 2018·2 cites·10 claims
- 1173US9443048B2Physical aware technology mapping in synthesisIBM·Filed 2014·Granted Sep 13, 2016·2 cites·8 claims
- 1272US9378326B2Critical region identificationIBM·Filed 2014·Granted Jun 28, 2016·2 cites·3 claims
- 1372US7269806B2Decoupling capacitance analysis methodIBM·Filed 2006·Granted Sep 11, 2007·4 cites·14 claims
- 1470US7987400B2Method for optimizing scan chains in an integrated circuit that has multiple levels of hierarchyIBM·Filed 2008·Granted Jul 26, 2011·6 cites·18 claims
- 1568US7346877B2Decoupling capacitance analysis methodIBM·Filed 2006·Granted Mar 18, 2008·3 cites·1 claims
- 1667US7827513B2Buffer placement with respect to data flow direction and placement area geometry in hierarchical VLS designsIBM·Filed 2007·Granted Nov 2, 2010·6 cites·17 claims
- 1766US9514265B2Congestion aware layer promotionIBM·Filed 2014·Granted Dec 6, 2016·1 cites·6 claims
- 1866US9495502B2Congestion aware layer promotionIBM·Filed 2014·Granted Nov 15, 2016·1 cites·11 claims
- 1966US8006213B2Optimization method of integrated circuit design for reduction of global clock load and balancing clock skewIBM·Filed 2008·Granted Aug 23, 2011·4 cites·13 claims
- 2064US10372866B2Data processing system to implement wiring/silicon blockages via parameterized cellsIBM·Filed 2017·Granted Aug 6, 2019·1 cites·20 claims
- 2164US9881100B2Scoping searches within websitesIBM·Filed 2013·Granted Jan 30, 2018·1 cites·18 claims
- 2264US9715572B2Hierarchical wire-pin co-optimizationIBM·Filed 2015·Granted Jul 25, 2017·1 cites·7 claims
- 2364US8799846B1Facilitating the design of a clock grid in an integrated circuitIBM·Filed 2013·Granted Aug 5, 2014·2 cites·20 claims
- 2462US7469399B2Semi-flattened pin optimization process for hierarchical physical designsIBM·Filed 2006·Granted Dec 23, 2008·3 cites·1 claims
- 2561US7921399B2Method for simplifying tie net modeling for router performanceIBM·Filed 2008·Granted Apr 5, 2011·2 cites·17 claims
- 2661US7752475B2Late data launch for a double data rate elastic interfaceIBM·Filed 2006·Granted Jul 6, 2010·2 cites·1 claims
- 2761US2025275250A1Staggered three-dimensional chip stackingIBM·Filed 2024·Application pending·0 cites
- 2858US10229238B2Congestion aware layer promotionIBM·Filed 2016·Granted Mar 12, 2019·0 cites·4 claims
- 2958US9443047B2Physical aware technology mapping in synthesisIBM·Filed 2014·Granted Sep 13, 2016·0 cites·16 claims
- 3057US9715565B2Physical aware technology mapping in synthesisIBM·Filed 2016·Granted Jul 25, 2017·0 cites·7 claims
- 3157US9710585B2Physical aware technology mapping in synthesisIBM·Filed 2016·Granted Jul 18, 2017·0 cites·14 claims
- 3257US7681169B2Process for managing complex pre-wired net segments in a VLSI designIBM·Filed 2007·Granted Mar 16, 2010·1 cites·15 claims
- 3357US7086026B2Decoupling capacitance analysis methodIBM·Filed 2003·Granted Aug 1, 2006·4 cites·4 claims
- 3456US11157586B2Scoping searches within websitesIBM·Filed 2017·Granted Oct 26, 2021·0 cites·21 claims
- 3556US9684757B2Cross-hierarchy interconnect adjustment for power recoveryIBM·Filed 2016·Granted Jun 20, 2017·0 cites·1 claims
- 3655US10140414B2Critical region identificationIBM·Filed 2016·Granted Nov 27, 2018·0 cites·3 claims
- 3754US9798847B2Cross-hierarchy interconnect adjustment for power recoveryIBM·Filed 2015·Granted Oct 24, 2017·0 cites·18 claims
- 3854US9552451B1Cross-hierarchy interconnect adjustment for power recoveryIBM·Filed 2016·Granted Jan 24, 2017·0 cites·1 claims
- 3953US9928322B2Simulation of modifications to microprocessor designIBM·Filed 2016·Granted Mar 27, 2018·0 cites·18 claims
- 4053US9690900B2Intra-run design decision process for circuit synthesisIBM·Filed 2015·Granted Jun 27, 2017·0 cites·8 claims
- 4153US8261224B2Computer program product, apparatus, and method for inserting components in a hierarchical chip designMALGIOGLIO FRANK·Filed 2008·Granted Sep 4, 2012·2 cites·21 claims
- 4252US9734270B2Control path power adjustment for chip designIBM·Filed 2015·Granted Aug 15, 2017·0 cites·8 claims
- 4351US9672321B2Virtual positive slack in physical synthesisIBM·Filed 2015·Granted Jun 6, 2017·0 cites·12 claims
- 4451US9672322B2Virtual positive slack in physical synthesisIBM·Filed 2015·Granted Jun 6, 2017·0 cites·6 claims
- 4551US2015143492A1System and method for identifying collaborators on a shared mobile deviceIBM·Filed 2013·Application pending·0 cites
- 4651US2015142886A1System and method for identifying collaborators on a shared mobile deviceIBM·Filed 2014·Application pending·0 cites
- 4750US9703910B2Control path power adjustment for chip designIBM·Filed 2015·Granted Jul 11, 2017·0 cites·12 claims
- 4850US9684751B2Slack redistribution for additional power recoveryIBM·Filed 2015·Granted Jun 20, 2017·0 cites·9 claims
- 4948US9697322B2Hierarchical wire-pin co-optimizationIBM·Filed 2015·Granted Jul 4, 2017·0 cites·12 claims
- 5048US7979838B2Method of automating creation of a clock control distribution network in an integrated circuit floorplanIBM·Filed 2008·Granted Jul 12, 2011·0 cites·12 claims
Showing the top 50 of 57 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →